Hi !
1). Equivalent Time Sampling - does it require an ADC without Pipeline delay. The latency of 4 clocks is it a problem in implementing EQT.
2). Regarding precise incremental delay of clock for next capture in EQT, one method is to use the readily available chip - programmable delay line IC. is there any other way to implement this delay logic say using logic gates or an FPGA. In my application I am interfacing a parallel ADC to an FPGA.
My target is to sample signals upto 100MHz.
Pl. share your experience(s),
JB Prasad
