• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 1138 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1278-HT ENOB

Rui Sousa
Prodigy 120 points
Other Parts Discussed in Thread: ADS1278-HT

Hi,

For the ADS1278-HT, which is a sigma-delta ADC, oversampled digitally filtered and decimated output, assuming high speed mode and fclk=32.768 MHz that means fmod=fs=fclk/4=8.192 MHz.

Looking at the datasheet, for full operating temperature range, pg 13 gives me SNR = 96 dB (@210 ºC), does this value apply for the BWNyquist up to fs/2?

So that, if my input signal BWsignal = 60 kHz I should get a process gain 10*log10(8.192*10^6/(2*60*10^3)) = 18.34 dB improvement from oversampling over the 96 dB spec?

The SNR = 96 dB from the datasheet accounts for quantization, thermal and clock jitter. Given the quantization and thermal are ADC's but jitter is from the external clock, how much is SNR from the clock used in the datasheet tests, so that I can take that parcel out and account for my own clock jitter? Does this even make sense?

After having answers for the previous questions, am I safe to calculate SINAD with the corrected SNR and THD as the

SINAD=-10*log10(10^(-SNR/10)+10^(-THD/10))

or do I have to make a correction (how?) because THD is not from a full scale input but -0.5 dBFS instead?

And then finally get ENOBADC from the SINAD. Phew! :-)

By the way, anybody knows of a good high-temp (200 ºC) clock for this ADS1278-HT ADC?

Sorry for all the questions, but I really need to clear this...


Thank you all and kind regards,

Rui

  • 0
    TI__Guru 66266 points

    Hi Rui,

    Thanks for your post and welcome to our forum!

    In theory, yes, SNR would apply all the way up to fs/2. We can only characterize SNR at select input frequencies due to the challenge of finding an input which is clean enough to test at these levels. Keep in mind that this refers to the digital filter output data rate of 128kSPS, not the modulator input sampling rate of 8.192MHz.

    Clock jitter is an important error source to consider in AC specifications. As long as the jitter is low enough to satisfy the timing specifications (i.e. tCPW, tCD or tCS, etc.), you will be able to meet the performance outlined in the device datasheet.

    For your reference, the equation below illustrates how clock jitter impacts SNR in delta-sigma ADCs:

    SNR = -20*log(2*π*fIN*tJITTER) + 10*log(OSR)

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Guru 66266 points
    Rui - I forgot to comment on your question about process gain. The spec listed in the datasheet already includes the process gain due to the oversampling ratio of the digital filter and is calculated as 10*log(OSR) (OSR = 64 in High-Speed Mode).
  • 0 in reply to Ryan Andrews
    Prodigy 120 points
    Hi Ryan,
    First of all thanks for the help.

    I was already preparing a reply about that missing question, but you beat me to it :)

    Anyway, how about the THD not being full scale? Any adjustment needed to calculate SINAD?

    Kind regards,

    Rui
  • 0 in reply to Rui Sousa
    TI__Guru 66266 points

    Hi Rui,

    THD is characterized at -0.5dB from full-scale in order to not over-stress the modulator. Pushing the inputs too close to the rails could result in other non-linear errors that degrade overall performance, similar to how amplifiers begin to distort the output as the inputs get closer to the supplies. For inputs less than -0.5dBFS, THD should remain constant.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 120 points

    Hi Ryan,


    Yes, I understand that. Am I to assume that SNR spec is measured also with the same VIN = 1kHz, –0.5dBFS same as THD?

    About the clock jitter, from your previous post, if I respect the timings, I should get similar SNR as in the datasheet?

    so the maximum allowed clock jitter should be <6,5 ns across full operating temperature range to get performance similar to the datasheet, correct?

    Kind regards,

    Rui

  • 0 in reply to Rui Sousa
    TI__Guru 66266 points

    Hi Rui,

    I believe SNR is also measured with a -0.5dBFS input, but let me verify that with a designer. You should meet SNR specs if you adhere to the timing requirements, but of course other factors can introduce noise into the system and degrade SNR. 

    The effect of clock jitter on tCPW is exactly as you drew it, although I expect a low-jitter oscillator to have jitter on the order of tens of ps. :)

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Guru 66266 points
    Hi Rui - SNR is actually calculated based on the peak-to-peak noise with the inputs shorted and biased to a mid-supply common-mode.

    Regards,