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How do I resolve the tension between minimizing stray capacitance and shielding sensitive nodes for ADS1291/1292?

Scott Brenneman
Genius 3295 points
Other Parts Discussed in Thread: ADS1291

The datasheet for the ADS1291/1292 advises us to "avoid stray wiring capacitance" for sensitive analog signals.  It also advises shielding those signals.  My instinct is to place the sensitive traces above a ground region tied to AVSS, and also flooding areas adjacent to the traces with AVSS, to minimize signal coupling from other sources.  However, the AVSS regions will increase the stray capacitance.  How do I resolve this apparent tension?  Or is the "stray capacitance" mentioned actually the capacitance to random external nets, and AVSS would therefore be okay to keep close?

I could also include guard rings, if there is an appropriate driven signal available to act as a guard.  Not being aware of any, I assumed AVSS would be the signal to keep close to the sensitive signals.

Thanks,

Scott 

  • 0
    TI__Mastermind 38745 points
    Hey Scott,

    Great question. I think this trade-off exists in essentially every application with tight analog signal integrity requirements. I think the answer is determined by the application. If the environment in which the product will exist is incredibly noisy, then signal shielding becomes a major issue. If the trace or wire length that the signal travels on is long, then stray capacitance between the signal and nearby potentials becomes more prominent.

    The idea of using guard rings is a good thought. If you're using the feedback enabled functionality of the RLD amplifier on this device, then you can drive the input signal common-mode voltage out on to the board - providing a signal of similar potential to your inputs to use as a guard ring voltage. Let me know what you think.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Genius 3295 points
    Hi Brian,

    The environment is somewhat noisy - Bluetooth module is on the same board. The trace from one electrode is quite short, a fraction of an inch, but from the other electrode it's just under 2 inches. What do you think about the shielding vs. capacitance trade-off in light of this info?

    The product is a chest strap, for fitness applications, so there's no right leg electrode. However, if there's a way to use the RLD amp as a guard drive, that might be good. The added power consumption of that amp doesn't look too bad, 5 uA Typical. How would I configure and connect that amp to act as a guard drive?

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    TI__Mastermind 38745 points
    Hey Scott,

    I think that the trace is short enough that capacitance probably won't be an issue. However, are there wires that leave the board to connect to the electrodes? I would be concerned about parasitics from the 2.4 GHz Bluetooth frequency making their way on to the signal lines. Make sure that there is some sort of anti-aliasing filter on your board in front of the inputs to the converter. A single-pole RC filter should do the trick as long as you are rolling off frequencies starting much lower than the Bluetooth signal frequency (you should ideally attenuate all signals outside of the converter bandwidth to avoid aliasing).

    If you still think that actively driven guard drive is necessary, then you'll need to consider a few things. First, the feedback system I mentioned before adjusts the RL voltage based on the other electrode voltages, but if the RLD is not connected, then it has no way of providing that feedback to the body so using that feature specifically would be pointless. You can still use the RLD amp as a driver of your common-mode voltage, however. I would recommend looking at Figure 52 on page 55 of the datasheet as it provides a helpful diagram of the functionality of the RLD amplifier.

    What is your common-mode input voltage? If its just mid-supply (AVDD+AVSS)/2, then you can use the RLD amplifer as a buffer of the internally generated mid-supply voltage. Referring to Figure 52, you'd want to open all the switches labeled RLDxP or RLDxN by setting the RLD_SENSP and RLD_SENSN registers both to 0x00. Then you'd want to close the switch labeled RLDREF_INT by setting bit 3 of the CONFIG3 register. Finally, you can power on the RLD buffer by setting bit 2 of the CONFIG3 register. The passive components R_EXT and C_EXT are just the feedback components for the amplifier, and the values shown in the diagram should suit your purposes.

    If your common mode input voltage is not mid-supply, but is generated by you on the board, then you can do exactly what I described above, except feed your input common mode voltage to the RLDREF/RLDIN pin and clear bit 3 of the CONFIG3 register. Then the voltage at the RLDOUT pin will just be your buffered common mode voltage.

    For an example of an application that uses the RLD amplifier as a shield driver for ECG cables, refer to the EVM users guide for this device. There is an output pin labeled "ECG_SHD_DRV" that is essentially the buffered output from the RLD amplifier. The buffer on the board that would actually drive the shield is labeled as "DNI" on the schematic, but one could imagine using an op-amp if the expected current draw would at any time come close to the specified short circuit current of the RLD amplifier. I hope this explanation gives you a decent guide for your design.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Genius 3295 points
    Hi Brian,

    Good to know about the capacitance. The topology has a single-pole low-pass filter in each electrode path, so I just need to choose the component values. Do you have recommended min. and/or max. values for either the R or the C in the filter?

    I lack the experience necessary to know if we need a driven guard, but I'd like to avoid that complexity. Common-mode voltage is mid-supply, and is set by a voltage divider for each electrode. I based the input circuit on the EVM, minus the respiratory and RLD parts. Briefly, it's like this: electrode -> series R (0 ohms for now) -> series C (2.2 nF) -> midpoint of CM voltage divider (10 M to AVDD, 10 M to AVSS) -> series R (for low-pass) -> shunt C (for low-pass) -> ADS1291 input. I can send you a screenshot if you tell me where to send it.

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    Genius 3295 points
    Also, you asked about electrode leads. Since it's a chest strap there are just contacts molded into the plastic housing which contact the board through springs. So, no leads.
  • 0 in reply to Scott Brenneman
    TI__Mastermind 38745 points
    Scott,

    No need to send the schematic. I believe I understand how you are setting the common mode. Given what I know about your board, I don't think guard rings are really necessary. For your RC constant to achieve good filtering, you can make it as small as you want as long as you do not noticeable attenuate in-band signals (in-band being DR/2). We also recommend attenuating at least 40 dB at the modulator frequency. You can always play with those components once you get the board as well.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Genius 3295 points
    Hi Brian,

    Given a specific RC time constant, are there practical limits on the R or C in order not to disturb the ADC operation? For instance, would too high an R result in the input current into the ADC perturbing the measurement?

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    Genius 3295 points
    I did some quick math. Fmod is 128 kHz, per the datasheet, which means that a single-pole LPF has to have a corner at 1.28 kHz or lower to get 40 dB down at 128 kHz. That limits our signal bandwidth to about 1 kHz, implying a max. useful sample rate of 2 kSPS. If we want a higher signal bandwidth we'd need a two-pole filter. Does that all sound correct to you?

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    TI__Mastermind 38745 points

    Hi Scott,

     

    In the datasheet electrical characteristics table, the input bias currents for a few different scenarios are listed. The offset in the voltage that you would see from the resistor would be due to that I*R drop across the resistor. In the table, it lists +/-200pA to be the maximum input bias current at room temperature with a 1.5 V differential input signal. Over a larger temperature rage, a typical current is +/-1 nA. Since you are setting your common mode at midsupply and ECG signals are on the order of mV in amplitude, I would expect your input bias current to be even less than those numbers.

     

    Your math looks good on the effective bandwidth constraint of your input if you chose an RC filter whose purpose is to provide 40 dB attenuation at the modulator clock frequency. You are correct that using a higher order filter would be effective at rolling off high frequencies quicker. Before you add that complication, however, what is the frequency range of your input signal? I would recommend using as low of a data rate as is necessary since that will maximize the device SNR.

     

    Regards,

    Brian Pisani

  • 0 in reply to Brian Pisani
    Genius 3295 points
    Hi Brian,

    That's helpful. I didn't know if input bias current told the whole story, since some ADC types have to charge internal sampling caps, and while delta-sigma is different, I didn't want to assume I knew all that was going on inside the converter. The bias current is low enough that it gives a wide flexibility in RC choices. I'm glad my math looks correct. I will have to consult with the other team members on the input signal frequency range. I know it's in the 1 kHz region, I just need to confirm it more precisely before finalizing the values. I agree that I'd rather avoid the added complexity of a two-pole filter.

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    TI__Mastermind 38745 points
    Hey Scott,

    Good observation. The actual modulator on this device is driven by the internal programmable gain amplifiers. The current you see at the input is essentially just the input bias current for the amp.

    Regards,
    Brian
  • 0 in reply to Brian Pisani
    Genius 3295 points
    Good to know. Say, in looking at the EVM schematic, there is a no-load capacitor across the N and P inputs. What would be the purpose of that, if used?

    Thanks,
    Scott
  • 0 in reply to Scott Brenneman
    TI__Mastermind 38745 points
    Hey Scott,

    That capacitor could be used as a differential anti-aliasing filter to improve the match in the cutoff frequencies for the single-ended filters if there was concern about the tolerances in the components creating noticeable differences in the cutoff frequencies. In most applications, the slight mismatch in the RC constants of the filters due to component mismatch is negligible.

    Brian
  • 0 in reply to Brian Pisani
    Genius 3295 points
    Hi Brian,

    I get it. I'll put it in there, since we have the space, and not load it.

    Thanks,
    Scott