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ADS1274 SLCK / CLK timing for best noise performance

Martin Damev
Prodigy 30 points
Other Parts Discussed in Thread: ADS1274

Hello together,

I've been using the ADS1274-EVM PDK for evaluation of the ADC performance and the results look promising so far. In a next step I would like to use the ADS1274 daughter board without the MMB0 in order to connect it to our STM32F407 (Cortex M-4) microcontroller eval board using the SPI-Interface. The power-supply issue of the ADS1274 daughterboard is no problem (IOVDD=+3.3V, DVDD=+1.8V and AVDD =+5.0V), however I have a question concerning the SPI communication between the ADS1274 and the microcontroller.

I intend to run the ADS1274 in high resolution-mode at a clockfrequency of fCLK= 27.0 MHz (provided by the on-board XTAL oscillator). The data output format used will be 001, in other words SPI, TDM, fixed mode and the resulting data rate 52734 Samples/s. If my calculations are correct the minimum SCLK frequency required would be: fSCLK= 4 * 24 * 52734 Hz = 5062464 Hz = approx 5.1 MHz (since all four channels need to be read).

My question is the following: In the ADS1274/8 data sheet it is stated, that for optimum performance the ratio CLK/SCLK shoud be 1, 2, or a power of 2. In a earlier post  I found in the TI community forum, it has been stated that for best noise performance not only the CLK/SCLK ratio is important, but also the phase.

Because of this requirements I intend to derive the SCLK signal from the CLK signal by using a frequency division of 4, e.g. fSCLK= fCLK/4= 6.25 MHz. This would allow to read out all four channels with a good timing margin. The SLCK signal of 6.25MHz frequency would be gated by an AND gate to allow the microcontroller to control the SCLK signal.Once the data is ready, the DRDY signal would cause an interrupt and then the microcontroller would initiate the data read out by starting the SCLK signal.

However the consequence of this setup would be, that the microcontroller would act as SPI slave, not a master, since the SCLK signal is not produced by the microcontroller. This a contradiction to earlier posts I found, where it has been stated, that the ADS1274 must always be the slave device and the uC the master device. However noise perfomance is critical in my application, therefore I seek the best solution concerning the communication between the ADS1274 and the microcontroller.

Any thoughts on this ? I would really appreciate some help on this issue.

Best regards,

Martin

Hello together, Sorry, I made a mistake in my previous post. With a clock frquency fCLK= 27.0 MHz , the SCLK frequency would be fSCLK= fCLK / 4 = 6.75 MHz , NOT 6.25 MHz.. Best regards, Martin

  • 0
    TI__Guru 66186 points

    Hi Martin,

    Thank you for your post!

    As you mentioned, the MCU is expected to act as the master device and produce SCLK for the ADS1274 in SPI Mode. Is there a way that you can provide the CLK and SCLK from the STM32F407? SCLK can be as fast as CLK, or perhaps there is an easy way to divide down the CLK frequency if you wish to run the SPI communication a little slower.

    Best Regards,