DAC3171 configuration problem

Hi,

I have a DAC3171 EVM powered up on my bench, but it may take me a little time to get it configured with the register values to match what you have listed and to see if i see the same behavior that you see.

In the meantime, i believe I see an error in the data sheet for register Config3 page 40.  You are setting the bits for datadlya and clkdlya according to the timing of the clock and data coming from your FPGA.   The bits 9:7 are shown as reserved but that is no true - these must be set with the same value as you set for datadlya.    These three bits are the delay value for datadlyb in the DAC3174 datasheet, but that is according to figure 2 of that datasheet.   In full word interface mode, there is no data 'a' and data 'b'. all the bits are used for channel a.  In reality, one of those delay fields set the delay for the upper 7 bits and the other field sets the delay for the lower 7 bits.  It is only in 7-bit bus mode for a two channel device that those bits are for channel 'a' and for channel 'b'.  You need to set bits 9:7 to be the same as bits 15:13 so that all 14 bits get the same delay.  Still - i wouldnt think that this issue would result in your lower 7 bits being static.  It may result in them being wrong, but not static. But please fix this and tell me what you see.  In the meantime I will look into your configuration.

Regards,

Richard P.

 

hi, Richard:
thank you very much for your reply.
I tried config3 as you suggested, but it still made any difference. I also tried to decrease the dataclk frequency to 5Mhz to look what would happen, while it was the same.
I also tried to use the config20 to do the static test, the results is shown below(directly binary work mode):
Code:0x2010(estimate 8mV,actual 42.4mV)
Code:0x2020(estimate 16mV, actual 42.5mV)
Code:0x2040(estimate 32mV, actual 41.2mV)
Code:0x207F(estimate 62.2mV,actual 42.3mV)
Code:0x2080(estimate 64mV,actual 103mV)
Code:0x20A0(estimate 78.1mV,actual 103mV)
From Above, it seems the lower 7-bit can not contribute to the output.
I also checked carefully my schematic and DAC31x1EVM_A-SCH which can be download from www.ti.com/.../dac3171evm. I found the only difference lay on the pin51 and 52 which are connected to +1.8VDAC in the EVM_A-SCH, but left open in my schematic. While you can see from the DAC3171 datasheet page13, it is recommended to left open.
Besides, i now use current-feedback amp OPA695 to convert the DAC current to voltage, it may be have problem at low voltage, and I am simulating its result.
Thanks again,
Regards,

jinling

Hi, there,
Today I tried to read out all the register contents to look at the working state of DAC. the results are shown below:
config0(address:0x00) value=0x0284;
config01(address:0x01) value=0x7033;
config02(address:0x02) value=0x3FFF;
config03(address:0x03) value=0xE380;
config05(address:0x05) value=0x0000;
config06(address:0x06) value=0x3B90
config07(address:0x07) value=0x8000;
config08(address:0x08) value=0x6000;
config09(address:0x09) value=0x8000;
config10(address:0xA0) value=0xF0A0;
config20(address:0x14) value=0xA03F;
config21(address:0x15) value=0xFFFF;
config22(address:0x16) value=0x063F;
config23(address:0x17) value=0x5144;
config24(address:0x18) value=0xC954;
config25(address:0x19) value=0xCFFF；
config127(address:0x7F) value=0x0049;

it seems the dac config is as what I want, but the lower seven 7 bits still can not contribute to the output, even I use the static test(config20).

regards,

jinling

Dear Richard,

Thank you for your reply.

Today I try the DAC A offset function( config8 address0x08), it actually works. That is the normal amplifier output which converts the dac current to voltages is 40mV, when I set the config8 with value 0x400F which can add output voltages by 7.3mV，the amplifier output is 48mV. but when I want to test the lower 7-bits of dac, it still can't contribute the output.

Hopeful the information will help you to diagnose the problem.

I am looking forward to get your reply.

Best wishes,

jinling

Hi,

What are you using to measure your voltage?  May i see what your amplifier section after the DAC looks lke please?

 

Regards,

Richard P.

Hi, Richard,

Thank you for your efforts.

I use the opa695 as the output amplifier and the dac desgin is same as the Ti file "Interfacing op amps to high-speed DACs,
Part 3: Current-sourcing DACs simplified" figure17.

Below are my dac schematic and Tina simulation files. I insert the file below, if it cann't be seen, could you tell your email or you can write email to mine(jx4g14@soton.ac.uk)

best wishes,

jinling

opa695_currentsource.TSCdac_design.pdf

Hi,

Again, what are you using to measure your voltage?  Does the equipment have the resolution to see the effect of the lower bits of the sample?  If you have a 1V full scale for example, one lsb of the 14 bit sample would contribute about 61 uV to the output.  You won't see the effect of the lsb's with an oscilloscope or hand held meter. 

Since you have looked at the offset field, can you use the offset field to move the output one lsb and measure (assuming you are using something with enough resolution to see the effect of 1 lsb.)  then use fhe offset field to move the output by 2 lsb's.  Then four lsbs.  Then 8.  In other words, put a '1' in each successive position of the offset field.  This will let you know if it is a measurement problem or a problem getting the lsb's of the sample clocked into the device. 

Regards,

Richard P

Hi, Richard,

Thank you very much for your kind reply.

I think I have found the problem, and the dac lower seven bits work well. The problem lies on the power up sequences. I use a clock generator cdcm6208 to generate the dac clk for DAC3171 and data clk to FPGA. In the past, the cdcm6208 would wait for 12ms to provide dac clk for dac3171, but during the wait time, the FPGA sented the configuration to the dac3171 by 4-pin interface. I suppose dac3171 would not work normally without the dac clk and data clk, even at last the dac clk and data clk would be provided to it. 

now I use the cdcm6208 register config-done signal as a reset signal to the dac3171 configuration module in FPGA, so the dac3171 registers will be configured after the data clk and dac clk are provided to the dac3171.

Thanks again.

Regards,

jinling

Hello Richard,

thank you very much for pointing out that datadlyb and clkdlyb have an effect also with the full word interface mode in the DAC3174! I've been pulling my hair sorting out strange problems with a design of mine and your comment immediately made clear what to do. I would *really* like to see a note about that in the datasheet. Ideally in all datasheets of this family, as they most likely all have the same requirement.

Something like *NOTE: If the full-word interface mode is used, datadlyb control the delays for data lines D[6:0], while datadlya control the delays for data lines D[13:7].* A good place for this note would be in the table on page 13 giving the setup/hold requirements vs. the delay settings and/or in the description of config3.

btw: Following the same scheme, does clkdlya control the delay on SYNC?

Best regards,
Philipp

Hi,

We recently put a new revision of the DAC3171 on the web dated January 2016.  It tries to make clear the relationship between the four delay fields and the input signals they affect.  The block diagram figures 66 -69 include text to indicate which delay field to use, and table 10 lists the input signals that the delay field affects.  The setup and hold table would also be a good place to make a note of this, thanks. 

Yes, the sync input has its delay controlled by clkdlya.   Where this still gets confusing is that when in 7bit bus mode on single channel, the clock input may be on what used to be the sync input pins 6,7 if the dual clock enable (dual-ena) is set, else the clock remains on pins 24,25.  So the signal DA_CLK in figure 69 could be on pins 6,7 controlled by clkdlya, or pins 24,25 which is controlled by clkdlyb depending on dual_ena.   Originally the register bit dual_ena was left off the single channel datasheet because it was thought it would not apply to a one channel device that would not need something called 'dual clock mode'.  But the bit still has an effect of the 1 channel device and we had to document that. 

The DAC3174 datasheet is in the process of being edited as well to add needed information such as this, as well as more paragraphs of text to describe the operation of the device.  Then the DAC3171 datasheet would again be revised to add the same textual descriptions.  Currently most of the details of how the device operates is found in tables and figures rather than a plain textual description of operation.

Regards,

Richard P.

Hi Richard,

this sounds like good news! Those DACs really seem to be good devices, but it was not too much fun to seek for the information in the datasheet. Glad to hear that this is being improved.
Thanks!

Best regards,
Philipp