I want to use high speed ADC12J4000 in my thesis. But, I need some information which I did not find in thedatasheet. For your receiving part of ADC, what is the aperture time (sampling duration not conversion ) of sampling and hold circuit ?
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I want to use high speed ADC12J4000 in my thesis. But, I need some information which I did not find in thedatasheet. For your receiving part of ADC, what is the aperture time (sampling duration not conversion ) of sampling and hold circuit ?
Ahmet and Cagri,
It is true that the sampling switches in the S/H require some amount of time to turn off and trap charge, so the process of trapping the signal charge does not occur instantaneously which results in a window of time during which the sampling process occurs. I believe this is the information you are asking about. The aperture delay reported in the datasheet is a combination of this charge trapping time and the propogation delay of the clock path from the clock input pins to the sampling switch and the delay through any buffers at the analog input. Unfortunately, we do not typically characterize the charge trapping time and other delays separately, so I cannot go into more detail. It is likely that the charge trapping time is highly dependent on PVT and the input clock frequency and edge rate, though I do not have data.
Regards, Josh
Ahmet,
Aperture delay does not necessarily limit sampling rate. As I mentioned before, the aperture delay is composed of a number of delays: The charge trapping time (let's call it sampling aperture), the clock path delay, and input signal path delay. The sampling aperture time would definitely limit the sampling rate (because the speed of the switches to turn on and off will limit the overall switching rate). The clock path and input path delays only skew the sampling instant relative to the input clock edge - they do not limit the switching rate.
Regards, Josh