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ADS1672 rising edge of multiple converters

Tobyn VanVeghten
Intellectual 700 points
Other Parts Discussed in Thread: ADS1672

Greetings,


I have an application where I am using multiple ADS1672s synchronized tightly together.  I daisy-chained the start signal to all the ADS1762s.  Due to reflections and discontinuities in the line, not all ADS1672s see a clean edge.  The rise time is always around 5 or 6 ns, but some converters see a glitch.  In all cases, the setup time indicated on page 8 of the data sheet is met.  The start edge always starts after the clock rising edge and any glitches have well settled out before the clock falling edge.  Does the ADS1672 care about the quality of the edge or is it simply looking for a level?  In my application, it is very important that these multiple converters be synchronized within 1 sample.  Do you think this will cause me any issues?


Thanks,

Tobyn

  • 0
    TI__Mastermind 23235 points
    Hello Tobyn -
    A couple questions:
    1. In the timing question are you referring to the edge of the START signal or the CLK?
    2. Are you using the same clock source/distribution to synchronize to all devices?

    START usually resets the digital filters and initiates conversions, so any glitches on the line may cause issues. Additionally, you want to make sure the devices have the same CLK signal, otherwise the different parts may sync at different times. There is a small section on synchronization on page 23 of the datasheet.
  • 0 in reply to Greg Hupp
    Intellectual 700 points
    Yes, I am referring to the START signal. I am sending the same clock buffered to each ADC. The clock signal is clean.

    Per page 23, it says the START signal is latched on the rising edge of the clock. This implies to me the behavior of START before the specified setup time does not matter. Is my interpretation correct?

    Thanks,
    Tobyn
  • 0 in reply to Tobyn VanVeghten
    TI__Mastermind 23235 points
    Hello Tobyn -
    Yes, the START is latched on the rising edge of the clock, so I believe your understanding there is OK. Based on the timing of the signal (Page 8), you probably want to ensure that the START signal transitions on or before the falling edge.
    One additional comment, it isn't clear exactly what you are seeing in terms of 'glitches' on the signal, but per page 15 (second paragraph under CONVERSION START), be aware that you can interrupt the current conversion if you issue another START signal.
  • 0 in reply to Greg Hupp
    Intellectual 700 points
    The rising edge of START is not a smooth transition from low to high due to EM reflections on the line. At about half the final voltage, there is a step (on some ADCs, possibly a slight dip by a few hundred millivolts), and then the signal continues up to the final voltage. I have plots of this, but I don't want to post them on the web.

    Thanks,
    Tobyn