sampling clock through long PCB trace

Xiang,

A 20 inch channel can cause the following performance issues:
- loss of clock edge rate leading to a reduction in SNR (due to jitter added within the converter)

- Greater possibility of aggressor signals coupling onto clock and degrading noise or spurious performance

A lot depends on your specific case: the amount of loss in your channel, the routing complexity and number of stubs and impedance discontinuities, and the co-location of aggressor signals.

The jitter added by the channel is generally only the base thermal broadband noise which impacts the performance more as the channel attenuates the signal, thereby reducing the signal to noise ratio of the clock. A clock signal is a static pattern, so the "deterministic jitter" generally only affects the edge rate but does compromise the periodicity of the clock. 

Best design practices include: use low-loss dielectric substrates, minimizing channel stubs (vias, connectors) and sharp turns, use tightly coupled differential routing with shielding reference planes (and via fence), and keep distance from noisy signals if possible.

Regards, Josh

Hi Xiang,

Avoid the routing of high speed clock signals from one module to another module in the PCB , as Josh mentined that it will leads to SNR degradation. It is better use connector & low loss cable metod to route the clock from one module to another module.
Regards,
Rajesh

Xiang:

We have various experience with FPGA layout and TI high speed ADC signaling. I would start by pointing out that for a 500MHz-1GHz sampling clock, we are actually talking about transmitting harmonics of the said clock frequency.

With that in mind we know we are considering signal integrity at roughly 5GHz-10GHz ballpark.

It is pretty obvious that for this type of clock distribution single end signaling will be extremely challenging. And I agree with all the points Joshua Carnes raised. So the most reasonable option is to use a LVDS sampling clock.

So ideally you should use RF connectors like SMA MCX or MMCX and high bandwidth high quality RF cables. Or high bandwidth connectors/impedance matched flex circuits(samtec offers quite a few options).

Although from my experience with roughly 500MHz signal and 20inch distance is not hard to achieve. But I propose you look into LVDS pre-emphasize or signal conditioning chips if the board is lossy or the connectors are not exactly high bandwidth.

Because LVDS is quite immune to common mode noises, so one of many likely ways your clk will be degraded is by some large swing, high speed digital traces, which was layouted physicly close and parallel to your clk traces. So avoid layouting the clk to say DDR3 traces and the like.

Some good layout practice will be like Joshua mentioned like reduce via stubs, etc. And prioritize your sampling clock.

Good luck.