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Problems encountered when evaluating ADC12J4000

KGY
Intellectual 300 points
Other Parts Discussed in Thread: ADC12J4000EVM, ADC12J4000

Hi,

I have encountered the below issues during evaluation of ADC12J4000. The ADC12j4000EVM
is connected to TSW14J56, using 4GHz external clock source , 2GHz to
LMKCLK and bypass mode. All input and clock are connected with filters.

1. I keep getting "read DDR to file timed out error" when capturing the data. I
have click on the "Instrument Options>Reset Board". i also tried the CPU reset button on board. the error still appears frequently.

2. when testing at eg. input frequency of 99 MHZ and 4GHz clk rate, i sometimes get many
high spurs ( as high as 30dB from fund) and sometimes good results. please see attached. what is causing the high spurs?

High Spurs captured:

Good capture:

 

  • 0
    TI__Mastermind 44680 points

    Hi KI

    Please make sure that your 4GHz and 2GHz RF sources are configured to use a common 10 MHz frequency reference. We normally do this by using the 10 MHz reference output of one generator as the reference input for the other generator. If these generators are not frequency locked there will be problems getting a consistent good capture.

    The bad capture shown above is what might be seen if the JESD204B transmitter in the ADC is not consistently aligned with the JESD204B receiver in the TSW14J56 board.

    Best regards,

    Jim B