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ADS131E06 Sampling rate

Gerhard Kreuzer
Expert 2600 points

Hi,

is there any formula to calculate the exact sampling freq of the converter knowing the internal clock frequency?

Is it a better choice to use an external clock to determine the sampling frequency?

How is the Synchronisation managed between sampled data and sending the data over SPI? I know there is the nDRDY Signal, so have I really get sample by sample using the nDRDY Signal as an Interrupt source for my processor?

I Need to get a fixed Count of samples, so I know the data length, and start reading with the first nDRDY, but how is the SPI clock synchronized to the data rate?

Any good tipps?

Thanks for helping.

With best regards

Gerhard

  • 0
    TI__Mastermind 23235 points

    Hello Gerhard -

    The equation information can be found on with the CONFIG1 register on page 15 of the datasheet.  That coupled with Table 4 (you can get the OSR by back-calculation, should get you the relationship between fCLK, fMOD, and fDR.

    In general, you will get better performance using an external clock, but this is dependent on your performance needs and the quality of the external clock.

    Data readback information is contained in the datasheet in a couple places.  A good place to start is the Data Acquisition on page 27.  The DRDY signal will indicate a new data point is ready for read.  It is then up to the processor to read the data or not.  Generally, the DRDY is using to start a DMA process that collects the data, but this is strictly up to the user.

    The SPI clock is a communication clock, so there is no synchronization between the SPI clock and ADC clock domains.  You want to make sure that your SCLK is fast enough to read all the data bits out before the next DRDY and that it is within the timing specs.

  • 0 in reply to Greg Hupp
    Expert 2600 points
    Hi Greg,

    thanks, but .... I read on page 15:

    fMOD= fCLK/ 2. Where fMOD= 1.024 MHz. Hu. So clock is 2.048Mhz, ok, I knew before.

    I have to use other sampling rate than 16kSPS, so I just want to Change the clock frequency, but stay within the Limits, written down in the data sheet.

    My guess: 2.048MHz / 2 / 64 = 16kSPS. so using 1.92Mhz / 2 / 64 will give 15kSPS. Maybe the text in the datasheet can be more clear once a day. Setting the DR bits to other values will give other sampling rates, but always 1:2 or vice versa for each step.

    I want to use a DS1086L clock Synthesizer. Output duty cycle is specified as 45 to 55%, no data about phase jitter or something else, but if you have a better choice, please let me know.

    Ok, so I have to read the data as nDRDY Signals new data, and I can use any clock which is fast enough to get the data in time and slow enough to stay within specification of the converter.. The processor has to Count the amount of data and than waiting for the next nDRDY pulse. Hope the DMA unit of my processor (and the Software Framework behind that all) can manage that. Will found out soon.

    With best regards

    Gerhard