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ADS1291 and the DOUT /DRDY pins

Elliot Greenwald
Prodigy 20 points
Other Parts Discussed in Thread: ADS1291

Hi all, 

On page 29 of the ADS1291's datasheet in the DOUT section it is stated that in read data continuous mode, the DOUT line indicates when new data is available and can be used to reduce the number of connections between the ads1291 and a system controller. I interpret this as meaning in read data continuous mode, you can bypass the /DRDY pin.  In my particular application pcb space is at an absolute premium, so any space that can be saved is a plus.  Thus, if possible, I would like to leave the /DRDY pin floating, and bypass it completely.

However, on page 36, from looking at Figure 43, it is not obvious to me how this could be possible.  From this figure it appears that after the first sample is read out, the DOUT idles at the value of the LSB of the last word transferred out.  The DOUT line seems to idle until a new set of clocks are issued.  So it seems that the /DRDY pin is still necessary to ensure proper timing.

I wonder if I've either A) misinterpreted the statement on page 29, B) misinterpreted Figure 43, C) missed something critical in the datasheet, or D) stumbled upon an error in the datasheet.

If anyone could help me clear up this issue I'd be very grateful.

Thanks,

Elliot

  • 0
    TI__Mastermind 18285 points
    Elliot,

    I'm moving your post to the correct forum.
  • 0
    TI__Mastermind 38745 points
    Hey Elliot,

    You have not discovered an error nor are you really misinterpreting anything. The DOUT pin can be used to indicate that new conversion data is ready. There is not much explanation in the datasheet because there are not too many applications that use that configuration (I can explain my theory as to why so few applications use it if you'd like).

    First, the CS pin must be held low for the entirety of any transaction for which you wish to use this feature (perhaps you'd like to hold CS low in hardware then you can bypass using that pin as well). When new data is ready, the DOUT pin will fall low to indicate that. Data will begin shifting out with SCLK. After collection, DOUT will remain at the level of the LSB. It will stay at that level until the next data ready indication if the LSB was high. If the LSB was low, DOUT will pulse and the negative edge will still be at the time that's consistent with a data ready indication.

    Does that explanation make sense? I apologize that there is not more information about this in the datasheet.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 20 points
    Thank you Brian, that completely clears it up! What is your theory as to why few would use this configuration? Is it because the dout pin needs to do double duty, i.e. both interrupt the host controller on falling edges as well as act as the spi data line?

    Thanks again,
    Elliot
  • 0 in reply to Elliot Greenwald
    TI__Mastermind 38745 points
    Elliot,

    You've got it. I'd imagine there are few microcontrollers out there with built-in SPI functionality that can also perform edge detection on the MISO line. To use this feature, it's likely that you'd have to use an FPGA and design your own SPI hardware to fit.

    Regards,
    Brian Pisani