How to set init_ state&jesd_ reset_n in DAC38j84?

Hi,

To reset the JESD core use the following sequence. Note that steps 2 and 3 should be separate SPI writes.

1. Set init_state to 1111 and reset_n to 0 - This resets the JESD core
2. Set init_state to 0000 to take the JESD core out of the initialization state
3. Set reset_n to 1 to take the JESD core out of reset

During start up, init_state should be held at 1111 and reset_n should be set to 0. After programming all clocks are running and the DAC is programmed, then take the JESD block out of reset using steps 2 and 3 above. While the JESD block is held in reset the SYNC signal will be held high. The SYNC signal will remain high after the JESD block is taken out of reset until the SYSREF signal is captured. After SYSREF is captured the SYNC signal will toggle low on the next LMFC cycle.

Regards,
Matt Guibord

Dear Matt,
Thank you very much for your help.

I have already succeeded in initializing the JESD204B link.
But each time after link is setup, i often see the read_empty error flag(bit0 of Lane FIFO errors).
What should i do to solve this error?
What is the cause of this error? So i can do some registers setting to avoid this error during start up.

Hi,

Great, glad to hear that you have the JESD204B link working.

The read_empty error is an issue with the error reporting from a FIFO block within the serdes core. The part will function just fine if this error occurs during start up. However, you should be able to reset the link upon seeing this error and it should go away - note that you have to clear the alarms first after reset. I believe proper sequencing of the JESD reset should avoid the issue. Can you clear the alarm after initialization or does the alarm always occur?

Regards,
Matt Guibord

Dear Matt, Thank you very much for your help.
I can clear the alarm and the alarm will not always occur.

Dear Matt,

 Now i met another problem.

 In config34(0x22), we can choose which sample(0~3) from JESD is selected for data path.

 Now i use the LMFS=2441.

 So in Lane 0, i transmitted: DA0[15:8],DA0[7:0],DB0[15:8],DB0[7:0].

      in Lane 1, i transmitted: DC0[15:8],DC0[7:0],DD0[15:8],DD0[7:0].

 

  For my case, which one is the sample 0 from JESD? Is it the DA0[15:0]?

                       which one is the sample 3 from JESD? Is it the DD0[15:0]?

Hi,

The JESD block has 4 outputs. The four outputs will corresponds to samples for DAC channels A, B, C, and D respectively. Therefore, you should also set register 0x22 to 0x1B1B to direct data from the JESD block to the appropriate DAC.

Regards,
Matt Guibord

Dear Matt,
Now I met a very strange problem.

The JESD204B link is established correctly and i send a fixed value(such as 0x4000) on the JESD204B link. The data format is set as 2's complement.
But there is no analog output from the DAC.
I can see there are no errors or alarms on the Lanes.

If i switch to the fixed value as Sifdac(config 0x2f & 0x30), there is analog output from the DAC.

What may be the cause of such strange situation?

Thank you.

Hi,

It's possible the link is not yet established - the JESD block will output the midcode value (0's in 2's complement) in this case. Have you issued SYSREF to the device? You can verify the link is being established by monitoring the SYNC signal during startup. You should see SYNC toggle low after SYSREF has been issued and then go high again. At that point if no errors are seen then the link should be established. 

If there still isn't an output then I may need to look at your configuration file.

Regards,
Matt Guibord

Dear Matt,
The SYNC signal acts as you say. After that point no errors are seen.

By the way, we use the sif_reset(bit 0 of Config 0x2, a transition from 0 -> 1 to reset the SIF registers). We don't use the RESETB pin of DAC chip. Is that ok?

the start of my configuration file is as below:
write Config 0x2 Data 0x0;
write Config 0x2 Data 0x1; // generate a 0->1 transition on sif_reset
write Config 0x2 Data 0x20c2;// set data format as 2's complement
and so on

Then how many time should we wait until the sif_reset operation is completed and we can start to write the Config 0x2 again?

Hi,

The RESETB pin MUST be toggled on startup as described in the sif_reset description. The DAC will not startup properly if RESETB is not toggled. This may be the source of your issues. Please see section 8.3 for the proper power up sequence.

Regards,
Matt Guibord

Dear Matt,
It is a pity that we don't connect the RESETB pin with FPGA in our PCB.
According to the datasheet(Rev B, March 2014), in the "Terminal Functions" table, it is said: this pin can be left open if not used.
Is the usage of RESETB pin a mandatory requirement?
Can we use the sif_reset to replace the function of RESETB?

Maybe we have to do a fly line in the PCB.

By the way, in section 8.3 for the proper power up sequence, the RESETB is toggled after the DACCLK generation. Is this requirement mandatory? Or can we simply toggle the RESETB pin after DAC chip power up?

Hi,

After thinking about this a bit, my feeling is that RESETB won't prevent the JESD link from starting. I would expect a possible degradation in performance though. RESETB cannot be replaced with sif_reset, so the comment about being left open is not valid. I'll need to get that updated.

Yes, the clock must be running before RESETB is toggled for proper startup.

Would you mind sending me your full configuration file for review?

Regards,
Matt Guibord

Dear Matt,
I double checked the full configuration file.

Yes, there was a bug in the configuration file that leads to the mis-establishment of JESD. After correction, the DAC can output analog waveform.

Thank you very much for your help during these days.

Dear Matt:

  I am still confused by the meaning of some configuration registers.

  Can you give me some help?

 

  In Config 0x24, for which case should we use the SYSREF to sync the clock dividers?

Hi,

SYSREF should be used to sync the clock dividers when trying to achieve absolute deterministic latency or when synchronizing with another device. Note that the device should be fully configured (JESD block in reset) and the clocks fully stable before setting config24. The next SYSREF pulse after setting config24 will sync the clock dividers.

Regards,
Matt Guibord

Dear Matt,
Thank you very much for your answer.


Can you tell me the config address of chip id for read back so that we can distinguish between DAC38j84, 37j84, 38j82 and 37j82.
And what is the exact chip id value of each type(4 types total)?

There is no detailed explanation in the data sheet.

Hi,

Unfortunately I don't have a good way for you to read back the exact chip type. This information is not stored in the chip.

Regards,
Matt Guibord

Dear Matt,
I can't understand why.

Since DAC38j84 and DAC37j84 have the same package, it is very hard to distinguish them.

Almost all the chips available in the market have a unique chip id.

Dear Matt,
Now i met a new problem.

I can't change the value of Config 0x5f and 0x60(which map Serdes lanes to JESD lanes).
No matter what i set the value, it seems that the POR default value always function.

Is there any special order to set Config 0x5f and 0x60? For example, should i set the Config 0x4a first?
In Config 0x4a, the definition of "init_state" is "During this mode, the JESD can be programmed".

Hello,

The programming of config0x5F and 0x60 (Serdes to JESD lane mapping) need to be done before the JESD initialization.

You may recall the conversation that you had with Matt regarding the startup procedure and taking the JESD block out of reset and init state. The SERDES to JESD lane mapping programming for config 0x5F and 0x60 has to be done any time before the JESD init/reset state.

-Kang

Kang, thank you very much.