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Problems with FIFO SN74v245-7PAG

Other Parts Discussed in Thread: SN74V245, PMP

I design a digitalization electronic system for an ultrasonic device.

Problem:
The FIFO SN74V245 goes first well after power-up. After a few (ca. 100) write and read cycles it begins to manipulate the output data. First its like an alias effect, then the second half of the data remains nearly constant. When a reset is performed it works well first but the problem repeats. The longer the power supply is present the shorter time it takes before the problem appears. The flags do sometimes not react at all, even though these are double buffered. They are then both on a low stage. My question is, if this is a known problem and if you could help me finding the source.

Steps Needed to Recreate Problem:
The FIFO is placed on a four layer board with three ground planes, nevertheless I think it could be a ground problem. There are no decoupling capacitors near by the device. There is probably no timing problem in the read or write cycles. It is used in the standard mode with double buffered asynchronous flags. It is not used in a depth expansion. The read clock is directly connected to an oscillator, whose output is decoupled to ground. The input signals come from an analog-digital-converter, these are ok. The frequency of the write clock is 40MHz, the one of the read clock 12MHz. The write and read progress do not happen at the same time but sequentially.

  • Relaying answer from Hirel group
    Based on his description of the problem I believe that the WEN or REN is not synchronous to the WCLK or RCLK.  Find out what is controlling the WEN and REN and what controls the edge placement with respect to WCLK or RCLK.
  • Hello,

    I'm using the SN74V245 fifo in my application, but it isn't working well.

    I'm using fifo in standard, asynchrouns, single register-buffered mode, so i conect the /fl, /rxi, /wxi to ground.

    After reset i have this configuration of flags: /EF , /PAE low,  rest high, so that's ok. But when i write to the fifo the /EF flag doesn't go to high,  /PAE goes high.

    I write while the /FF flag is high. Then I read the fifo while the /PAE flag is high and when /PAE goes low, the /EF flag goes high.

    Best regards,

    Przemek

  • Przemek,

    Sorry I was out of the office.

    The behavior appears that the device is in FWFT mode.

    Could  you describe your power up and reset sequence in detail?

    Are FLn,RXIn, WXIn literally tied to GND?

    Do you meet all the timing requirements shown in figure 1?

    RENn, WENn, LDn high for tRSR after RSn deassertion?

    Regards,

    Wade

  • Hi,
    I found a solution. The /EF flag is update synchronously to RCLK and I used bad interface to drive the fifo. When I'm using another interface, everything is fine.

    I have a one more question.
    I use this fifo to storage the data from adc, and I want to use a microcontroler, which will get the data from FIFO to another memory or computer(via usb).
    So which microcontroler do you recomendate? I would like to have 500MB external sdram to storage the all samples.

    Best regards

    Przemek

  • Przemek,

    I would recommend looking at the embedded processor launch page to narrow down your requirements.  The FIFO products are supported out of the High Reliabillity group, so I do not have as good a visibility to all processors.

    http://www.ti.com/lsds/ti/dsp/embedded_processor.page

    Once you have a processor family in mind, you can post to the E2E page supporting that project for confirmation or clarification.

    One of the ARM devices likely will be your best choice.

    Regards,

    Wade

  • Hi

    We have similar problem with SN74v245, could you tell me what interface you using now and what was wrong in previous one? We read data from fifo using PIC32MZ PMP interface.