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Question on ADS1274 SPI Interface (Second question)

Hak-Jin Jeong
Intellectual 350 points
Other Parts Discussed in Thread: ADS1274

I already posted my question(Question on ADS1274 SPI Interface) and got the answer.

and I have second question. that's why I posted again.

If D-flip-fop is used, consequently DOUT1 will be delayed by half period of SCLK.

How does/shoudl SPI master deal with this delay to get the right data?

Is there some example code?

Thank you for your help in advance.

Best Regards

Hak-Jin Jeong

  • 0
    TI__Guru 66206 points
    Hello Hak-Jin,

    Fortunately, this technique does not require you to make any changes to your processor. The data on DOUT1 is delayed by (or "preserved" for) 1/2 SCLK period longer; however, the original SCLK input is still used by the processor to latch in the data on the rising edge as always.

    Best Regards,