ADC12J4000 status bit about ALIGNED and REALIGNED

Hi Toshi

1)  As stated in the description, the ALIGNED bit will be set after enabling the JESD204B encoder, when the internal multiframe clock has been established by the external SYSREF.

2)  Regarding REALIGNED.

The div8 clock is an internal clock utilized in several different portions of the device.

ALIGNED only indicates that the multiframe clock has been aligned by SYSREF. REALIGNED indicates if the div8, frame or multiframe clocks have been shifted from the previous alignment. With a periodic SYSREF, the REALIGNED bit can be used to verify that the SYSREF to DEVCLK setup and hold timing is being met consistently. If this timing is adequate SYSREF will always be captured on the same DEVCLK edge and REALIGNED will not be set. If setup or hold is marginal then SYSREF may be captured one DEVCLK edge earlier or later. This will shift the multiframe or other timing earlier or later which will cause the REALIGNED bit to be set. This can be used as an additional indicator when adjusting the SYSREF delay timing for optimal alignment with DEVCLK. See the datasheet sections on SYSREF and Multiple ADC Synchronization for more information.

The REALIGNED bit can be set at any time that the SYSREF receiver and SYSREF processing are enabled.

Yes, the REALIGNED bit is part of the frame alignment process.

Best regards,

Jim B