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DAC3161 configuration problem with xilinx FPGA

Srinivasa Rao Mandala
Prodigy 10 points
Other Parts Discussed in Thread: DAC3161

Dear sir/madam

I am trying to configure the dac3161 as follows, made the sdenb is zero during the instruction cycle(1 byte) and data transfer cycle(two bytes), once this serial data passed to the dac, made the sdenb is one. By refering the table 6 of dac 3161 data sheet,fed the serial data to the sdio pin-44,instruction cycle data as 0x00  and the data transfer cycle 0x44fc, SCLK is10MHz,txenable is high, dac data is continous sin data and dacclkp,dacclkn,dataclkp,dataclkn is 100Mhz. With these conditions i could not see the dac out put. I dont know where iam doing wrong.  

Please help me to do a correct configuration of DAC3161.

With regards 

Srinivasa Rao

  • 0
    TI__Mastermind 29220 points

    Hi,

    There is no way i could tell what is wrong with such little information to work with.    You are trying to configure the DAC by way of a SPI write - do you know if that is working correectly at all?  Usually i like to determine if my SPI is writing correctly by writing to something that has obvious results such as a powerdown bit, but i don't see that bit in this device.  So instead i would look at a register such as Config12 and see if i can write a value of my choosing in that register and read back the same value.  And that after a reset pulse to the reset pin that i can read the expected default value.  After that works, then i know i can configure the DAC according to the Table6. 

    The DAC3161 requires a hardware reset to the reset pin before it can be counted on to operate as expected. And then read the alarm values in registers associated with the FIFO and clear the FIFO alrams if needed.  And make sure the alarms don't set themselves again indicating some config problem.   If there is a steady output instead of the expected waveform, check that the register bit for constant output is not set.

    Regards,

    Richard P.