Missing 5402.ini file for TSW1400EVM

Hi,

Do you have an ini file for ADS5401-09 and a corresponding device selection when you run HSDCPro?  There are many device part numbers in this family of ADC but one ini file to support the family. 

Regards,

Richard P.

Hi Richard,

I found an ADS5401-09.ini file in the "\1400 Details\ADC files" directory for the 1400 card, but don’t find a similarly named .rbf file when I look in the “Download Firmware” pull down menu. Any suggestion on which .rbf file would be compatible with the ADS5402EVM?

Fred M

Hi,

That's not how it works.  In that ini file the top line is Interface name="ADC_SAMPLE_WISE_2CH" and there is an rbf file there by that name.  Most of the time when an rbf file carries the name of the device it is because that device has a unique format that needs its own unique firmware.  But families of devices that have similar formats can share a firmware.  This whole process should workseamlessly for you.

The way it works is that the HSDCPro upon launch will go get the list of ini files and make from that a list of devices that you can select from the drop down list.  Adding a new ini file and relaunching HSDCPro will result in a new device that could be chosen.  In each ini there is the name of the firmware that should be loaded for that device.   Each firmware has a unique ID number hardcoded in it in Verilog, and HSDCPro reads that ID number and does a lookup on that number and displays the name of the firmware in the lower right corner of the GUI.  There is an IID_lookup csv file that shows the mapping from ID numbers to the names of the firmware.   You may notice in selecting a device that there are diamond shapes to the left of some of the device selections.  These are device selections that use the same firmware as is currently resident in the FPGA and switching to one of these selections does not trigger pushing the firmware down to the FPGA again.

Regards,

Richard P.

Hi Richard,

Thanks for the explanation. I set the Select ADC to ADS5401-09, and now see the Interface Type = ADC_SAMPLE_WISE_2CH in the lower right of the GUI screen matching the first line of the ADS5401-09.ini file. After setting the ADC Output Data Rate to 800MHz, and the ADC Input Freq to 100MHz, I click on the “Capture” button. The Status line in the lower left shows “Start ADC to DDR” for about 10 seconds then I get a popup window “Read DDR to file TIMED_OUT_ERROR”. Is this another problem or does it still point to a setup file incompatibility?

Fred M

Hi,

The most common reason for the capture to time out is that there is no data clock in to the Capture Card from the ADC EVM.   This may be because of something simple such as no clock to the SMA on the ADC EVM, or no power to the EVM, or an incorrect configuration of the ADC through the SPI port into the configuration registers of the ADC.   The ADS5402 should have a reset either by hardware pushbutton or software GUI button click (I do both) and then use the GUI to enable the autocorrection if desired and make sure the HP1 button is set.   But there are no required SPI writes from the GUI to make the ADC have an LVDS output clock to go with the sample data - that should power up ok and at least allow the TSW1400 to capture.   Unless you did a SPI operation to powerdown the ADC or something like that.

The way the capture works is once the EVM and TSW1400 are set up, pressing that capture button initiates the HSDCPro to tell the TSW1400 to capture the desired number of samples from the ADC into the DDR memery and then pass that captured data back up the USB to the PC for processing.  If there is no LVDS clock to go with the sample data from the ADC, then obviousy the desired number of samples could never get captured into memory.  We have about a 15 second timeout built into HSDCPro for that occasion.

There is a bank of 8 LEDs on the TSW1400, and the one USER_LED3 will indicate that the PLL in the FPGA is locked to the LVDS data clock from the ADC.  If the LED is not lit, then the FPGA does not see such a clock.  In that case you may need to probe the hardware to see if the ADC is outputting an LVDS clock, and if the ADC is seeing the sample clock into the ADC, and that the ADC has all its correct voltages on the supply pins. 

If the clocking is presetn and the capture still times out then we will have to consider other things.  Like whether 100Msps is too low for the PLL in the firmware for the ADS5402 since this family of devices do operate up to 900Msps.  There will be some such sample frequency that becomes the lowest supported sample rate, but i would not have expected 100MHz to be a problem.  Trying something like 300MHz for a capture would tell us if this is the problem or it is something in the setup.

Regards,

Richard P.

Richard,

I did get the EVM combination working last night. As you mentioned it was exactly the missing clock to the ADC SMA connector that was the problem.

Many thanks for your help in getting me up and running with the project!

I do have another question about a sweeping variable clock that the application has to deal with. I'll post that question on another string as it may be a helpful topic for someone else. Would much appreciate your input on that upcoming post as well.

Best regards,

Fred M