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ADC128S102 Channel Sequence and SPI Clock Symmetry

Clint Brown
Prodigy 20 points
Other Parts Discussed in Thread: ADC128S102

I plan on designing in a ADC128S102 in a sampled data acquisition system. The overall sampling rate is 200 kHz (5 us) and there are 3 signals which must see this 200 kHz rate, and 4 signals which will see 1/4 this rate. The channel sequence I plan on using is 0-1-2-4, 0-1-2-5, 0-1-2-6, and 0-1-2-7, being driven by a 14.65M clock. This gives me 4.5 us conversion time. I set up the following sequence - can anyone tell me if I am close?

Next question - to achieve the 14.65M clock I am dividing a 102.5M clock by 7 which will result in a 3/7 asymtery on the SCLK. This exceeds the data sheet limits of 40/60% - which at 16M are 25 nS and 37.5nS. However since I am reducing the clock frequency from the maximum the minimum high/low times will be 27 nS/41 nS. Is the pecentage high/low regardless of frequency or is it based on minim high/low times?

  • 0
    TI__Mastermind 25990 points
    sorry for the confusion, I am reading between the lines a bit, but I think you are understanding correctly. what you are proposing is not a problem. the duty cycle limits are driven by the highest clock frequency of 16MHz, but even then, we have headroom.
    Chuck
  • 0 in reply to Chuck Sins
    Prodigy 20 points

    This is 1/2 questions answered. Can you answer the first question please? Been a week already!

  • 0 in reply to Clint Brown
    TI__Mastermind 25990 points
    sorry, I got caught up in your other question, your picture shows that you are understanding how the addressing scheme works. my only comment is your first conversion result. you will get channel zero after first power up because that is default register setting. but after power up, the address holds what what written into it during the last conversion. your calculation for conversion time also makes sense.
  • 0 in reply to Chuck Sins
    Intellectual 510 points
    Hello chuck ,

    There is a Question:
    I should give the ADC two bytes (first is the Register channel Command) and second Send Byte is dummy data , and I will get the answer of the wanted ADC channel after this two bytes is sent , Is this True?
  • 0 in reply to ibrahem mostafa
    TI__Genius 16890 points

    Hello,

    You will send 16 clocks to the ADC.  The only data bits that matter are the ADD2, ADD1 and ADD0 bits.  All the other 13 bits are don't cares and can be set to 0 or 1. 

    For example:

    Power on the device.

    Send 16 clocks with the DIN data 00 001 00000000000, you get the data on DOUT for channel IN0 (default power on channel) and set the next reading for data from channel IN1.

    Send 16 clocks with the DIN data 00 010 00000000000, you get the data on DOUT for channel IN1 and set the next reading for data from channel IN2.

    And so on.

    Mike