ADS8556 REFC Pins and capacitors?

Huseyin Dogan

Other Parts Discussed in Thread: ADS8556, DAC8728, DAC8728EVM

Hi Tom,

I wanted to continue with the other thread (Making own ADS8556 card?) but I could not see any "Reply" button. So I decided to open new one. After a long while I am continuing to design my adc-dac card. I have new questions;

1- In ADS8556 manual at page 13 there are expressions for the REFC_A (pin 54), REFC_B (pin 56), REFC_C (pin 58) and REFIO (pin 51). "Connect a 10 uF ceramic decoupling capacitor between this pin and pin 53 (or 52,55,57)". Also there is an article written by Matthias Taenzer (Texas Instruments' Nyquist ADC group) at below link which also supports same layout. But when I looked at the ADS8556EVM gerber files, I realized that Pins 52,53,55 and 57 are connected directly to the top GND plane, not to the capacitor leg. So I am confused. Which layout gives best result?

http://www.power-eetimes.com/en/optimizing-sar-adc-performance-by-proper-pcb-layout.html?cmp_id=71&news_id=222901086&page=3

Layout1

Layout2

2- Could you please glance my layout for one ADS8556 chip? (There will be one more ADS8556 and DAC8728). I used 2 layer board. Bottom layer is almost dedicated for AGND and DGND. Only the area under the chip is a little splitted due to the lack of AVDD layer. I placed 100 nF decoupling capacitor just under the chip. I used one capacitor for adjacent AVDD pins (34-35, 40-41, 46-47) as ADS8556EVM. AGND and DGND are connected only at one point at the bottom layer. Does this layout give me acceptable results?

Bottom and top copper together

Only Top copper

Only bottom copper

Thanks alot for your answers

Best regards

over 10 years ago

0 Tom Hendrick over 10 years ago

TI__Guru**** 182601 points

Hi Huseyin,

Sorry for the delay in getting back to you, i am traveling this week. Both boards showed similar performance. I will look over your layout and get tback to you as soon as I can.

0 Huseyin Dogan over 10 years ago in reply to Tom Hendrick

Prodigy 40 points

Hi Tom

While i was waiting for your answer i decided to design DAC8728 layout. (There will be 2 ADS8556 and 1 DAC8728 chips on my card) But I was disappointed when I saw the pin configuration of DAC8728. It is different from the ADS8556. ADS8556 pin configuration is suitable to make separate analog and digital sections easily because analog and digital pins are aligned at the different sides of the chip. Also a recommended layout is given in the manual and it is applicable with a two layer board. But with the DAC8728 chip it is not possible to make separate analog and digital sections on a two layer board (at least i could not). Both AGND and DGND planes at the bottom layer have to be broken to route power (AVDD, AVSS, DVDD and IOVDD) and signal traces. So i decided to turn my to layer decision to four layer. Probably it will be from top to bottom : 1.signal 2. Separate AGND and DGND 3. Separate power 4. signal. But i have a problem. I read alot of articles about proper layout consideration. I have learnt one important basic: return path of a signal traces prefers route just under the signal trace. So for minimum loop problems a gnd layer should be placed just under the signal trace all around the board. If a signal trace jumps to bottom layer (by via) and on the way until to the top layer again (by via) there will be power plane just under the signal trace. In other words there will be a power plane between the gnd plane and signal trace. Isn't it a problem. If yes; can some portion of power layer be used for GND plane to make a return path for bottom layer signal traces? Also is there gerber file for DAC8728evm? Why isn't there a layout recommendation for DAC8728 as ADS8556?

Thanks alot for your help.

Best regards.....

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ADS8556 REFC Pins and capacitors?