Hi,
There is a" IDAC VOLTAGE COMPLINCE" when being "AVDD=5V", at ADS1248(SBAS426G) page22 Figure47/48.
I want the "IDAC VOLTAGE COMPLINCE" special quality chart when being AVDD=3.3V.
Can you request it?
Best regards
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Hi,
There is a" IDAC VOLTAGE COMPLINCE" when being "AVDD=5V", at ADS1248(SBAS426G) page22 Figure47/48.
I want the "IDAC VOLTAGE COMPLINCE" special quality chart when being AVDD=3.3V.
Can you request it?
Best regards
Hi, Wu-san
I thank you for your comment.
That there is no available documents, I understand.
Although it has the same question, and IDC characteristics when VDD = 5V, Is there a difference between the IDC characteristics of VDD = 3.3V?
If there is a difference, can you tell us that?
Best regards
Hi
ELECTRICAL CHARACTERISTICS of ADS1248 all have been defined by the AVDD = 5V.
Or characteristic data there is when it was defined in each item AVDD = 3.3V?
For example, INL = 15ppm (Max) → AVDD = 3.3V: INL =?
Overall, do you can determine the direction of AVDD = 5V is a good performance than at the time of 3.3V?
Best regards
Cafain-san,
I was about to point you to a response that I just wrote, but I realized that you are not on the same forum. I believe that this is for a customer in Japan, so it may be from the same customer, but through one of the TI FAEs. I'll just copy my response here:
*****
For 3.3V operation there is some characterization data, and can be found in the datasheet.
Tables 5 and 6 show the noise at low voltage operation (AVDD=3V) and you can see that the noise goes up almost by 2x. That is almost 1 extra bit of noise off of the resolution. Additionally, there are some noise histogram plots in Figures 7 and 8.
There are also offset and gain plots for drift over temperature for low voltage operation. While they do not match exactly, they are very similar and it looks like the low voltage does not affect either parameter.
For the INL, I don't see any data, but since the offset and gain error do not change much at low supply, it is likely that the INL does not change much either at low supply since the gain and offset are often generated from the INL measurement.
I would note that using the IDAC at low voltage might be difficult with the compliance to the positive supply. If you look at Figures 47 and 48. The compliance of the IDAC current at low voltage would be similar. It would be like taking the x-axis for Figure 47 and 48 and subtracting 1.7V (from the difference between 5V and 3.3V). It may not matter if the customer uses a simple ratiometic measurement because the same current goes through the measurement and the reference resistor. However with more than 2 wire RTDs, the match between the currents may have more error when the IDAC output voltage is close to the rail (where the currents starts to fall off on Figure 48.
*****
Joseph Wu