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DDC112

Nathan Jones
Prodigy 10 points
Other Parts Discussed in Thread: DDC112

Hello to all, I'm new here so I hope this is the proper place for this question. I would appreciate any help you all can give me!

I am currently working with the DDC112, dual current input 20-bit ADC, and had a question about the line in the datasheet (pg. 9) that says:

" For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended CONV toggle withiin +/- 10 ns of the rising edge of CLK."

Elsewhere in the data there are certain timing values (such as the time to complete one ADC conversion) which increase or decrease based on the system clock, CLK. Is the same true for this constraint? Does running the DDC112 at a clock speed slower than the nominal 10 MHz (but still within the specified range of 1-12 MHz) loosen the constraint that CONV has to toggle within +/- 10 ns?

  • 0
    TI__Guru* 97465 points

    Nathan,

     

    No, lowering the clock rate does not change the constraint that CONV should trigger within 10ns of the rising edge of CLK (to get the best noise performance). It's an attempt to line up the rising edge of both the CONV and CLK lines.

    I believe that the timing is to isolate some noise that may get coupled into the signal from the CONV line.

     

    Joseph Wu