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ADS1198 Chest Electrode output is missing

umamaheswar peta
Expert 1370 points
Other Parts Discussed in Thread: ADS1198

Hi,

We are using ADS1198 device for one of our medical application.

When we are testing in our customized board and we are able to get below output's.

Lead 1 output is successful.

Lead 2 output is partially okay

Chest Electrode output is missing.

Kindly find attached schematics FYR, and let me know if any modifications required.

Rgds,

Uma MaheshSCHEMATIC1 _ PAGE8.pdf

  • 0
    TI__Mastermind 38745 points
    Hello Uma,

    Your connections look fine. What exactly is happening when you say that the chest electrode output is missing? Does the data return as zeros? Or does it come back as noise? What does the Lead II output look like? My gut feeling is that this is most likely a register settings issue. Can you send me all of your register settings?

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Expert 1370 points
    Hi Brain,

    Thanks for your mail.

    Please find below the Register Configuration Details

    CONFIG1 = 0x04,CONFIG2 = 0x10,CONFIG3 = 0xDC, LOFF = 0x03,
    CH1SET = CH2SET = CH3SET = CH4SET = CH5SET = CH6SET = CH7SET = CH8SET = 0,
    RLD_SENSP = 0,RLD_SENSN = 0,
    LOFF_SENSP = 0xFF,LOFF_SENSN = 0x02,
    LOFF_FLIP = 0x00,
    LOFF_STATP = 0XF9,LOFF_STATN = 0x00,
    GPIO = 0X00,PACE =0X00,RESP = 0XF0,
    CONFIG4 = 0x02,
    WCT1 = 0x0A,WCT2 = 0xE3
    While using this configuration we face the following issues,
    1) Leads output:

    Lead 1 output is successful.
    Lead 2 output is partially okay
    Lead 3 output is missing

    Kindly provide us necessary solution to get the outputs properly.

    2) DRDY Output pin:

    Output pulse is not generated in our board which is under development. However, the output is normal with your board.

    Kindly let us know how to control the pin or will the chip control the output itself.

    3) V reference:

    Kindly let us know if we need to give internal or external V reference; which is the best out of the two?
    If we external reference is used, what is the value of V reference (+ve and –ve).

    4) Clock Pulse:

    We are not getting the internal data; How to control the clock pulse externally?

    5) SPI Protocol:

    Start pin –
    Single mode – Is manual start to be given or OP code should be given?
    In which will the data will be accurate – single or continuous mode?

    6) ADS 1198:

    How to control the chip and also to identify whether the chip is working or not?
    7) Testing SPI Communication:- Using RREG register
    While trying to read the value of configuration registers over SPI, there is no issues on the development board.But we couldnt read the value of the registers on our own board.

    Kindly Suggets.

    Thx&Rgds,
    Uma mahesh
  • 0 in reply to umamaheswar peta
    TI__Mastermind 38745 points

    Hello Uma,

    Looking at the register settings, there doesn’t seem to be anything amiss. I will try to answer your questions one by one.

    1. I’m still unclear on what is meant by “partially ok” and “missing”. What exactly is happening?
    2. If the START pin is held high, the modulator will be constantly converting and the DRDY pin will toggle without any software interaction. If the START pin is held low, the modulator will be controlled by the START and STOP SPI commands. In this case, the device will power on in a non-converting state and the START command will have to be issued to start the modulator.
    3. There are advantages to both topologies. With the internal reference, there is no extra hardware design to be done, board space is saved and less power will be used versus including an extra IC or two to generate and buffer the reference. With an external reference, you might be able to achieve better noise and drift performance. If an external reference is used, it can theoretically be any range within the power supply rails. In the characteristics table on page 4 of the datasheet, however, we indicate a typical setup will have VREFN connected to AVSS and VREFP connected to either a voltage near 2.5 V or near 4 V, depending on the supply range.
    4. To what exactly is this referring? Are you trying to trying to have the internally generated clock appear at the CLK pin as an output? There is a handy truth table on page 25 of the datasheet that describes the different clocking configurations.
    5. Refer to my answer to question 2 on how to control the converter with the START pin versus SPI commands. If you stop and start the modulator every time you want to retrieve one sample, it will be neither efficient nor particularly accurate since the digital filter will not be settled to the correct value. If the device is converting, there will be no difference between the data received in RDATAC mode or in SDATAC mode. The only difference in those modes is the protocol for retrieving existing data.
    6. Seeing DRDY toggle is probably the easiest way to determine that the device is in a good state.
    7. This suggests an SPI communication issue. My suggestion would be to look at your protocol on the oscilloscope or with a logic analyzer and see if the right command is being given, the timing is good, and that the CS pin is low for the entirety of the transaction.

    Regards,

    Brian Pisani

  • 0 in reply to Brian Pisani
    Expert 1370 points

    Hello Brain,

    As per your previous advice we have tested SPI communication with Development Board and OWN module.

                         The chip select pin of SPI protocol is getting low through Software control in Development Board but not in OWN module. We have tested both in Software as well as in Hardware side. But unfortunately we could not identify the problem. Please give us some valuable suggestions to resolve the issue, and also please find attached video for the output wave-forms we are getting.

    Thx&Rgds,

    Uma MaheshECG.zip

  • 0 in reply to umamaheswar peta
    TI__Mastermind 38745 points
    Hello Uma,

    The chip select pin problem definitely sounds like a firmware issue. You'll likely have to dig into the code to figure out why the microcontroller doesn't pull that pin low.

    For the waveforms, it does seem that the Lead II display shows a flat response in between QRS complexes. However, I tend to believe this is also a software or firmware issue. To verify, implement a way to read the raw data that is being collected from the ADS1198 and compare it to the data that gets output on the display.

    As for the last channel not displaying, I also recommend looking at the software for the issue. I would start by verifying that data is being read from that channel and then tracing its path through the code to the display.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Expert 1370 points
    Hi Brain,

    Thank you so much for your support.

    Problems Rectified:
    CS pin is pulled low by software. SPI communication is also been tested by reading the default registers, which are configured in the ADS1198 module and it is working fine.
    Needsome more Clarifications:
    Here, we know that DRDY pin toggles only when we start the conversion.Then How does this generate the clock. Either depends on the conversion time or else by any other concept. And how to control the clock which is generated by the DRDY pin.

    Rgds,
    Uma mahesh
  • 0 in reply to umamaheswar peta
    TI__Mastermind 38745 points
    Hey Uma,

    No problem! To be clear, you are talking about the master clock, correct? The master clock on this device can be supplied externally at the CLK pin or can be generated by an on-chip oscillator. The device will pick one based on the state of the CLKSEL pin. On this device, the internally generated master clock has a frequency of 2.048 MHz. The clock is divided to produce the modulator clock which synchronizes modulator sampling. This device samples at 128 kHz. Then the oversampling ratio that you set in bits [2:0] of the CONFIG1 register will set the amount of decimation that determines the output data rate. The DRDY pin will have a negative edge at the data rate frequency.

    If an external clock is supplied and selected, the same thing happens except with the clock you generate. That also means that if the external master clock provided is not exactly 2.048 MHz, then the output data rates will not be exactly 125 SPS, 250 SPS, 500 SPS, etc. The maximum and minimum bounds on the external clock frequency can be found in the electrical characteristics table.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Expert 1370 points

    Hello Brain,

    All the problems are sorted out. DRDY(Data Ready) pin in ADS1198 is working fine with the clock of 500hz.

    Need clarifications on below:

     

                  We are getting lead-1 and lead-2 waveform in our own board. The waveform is good only  for some duration once if spike appears the whole waveform looks like noise.

     

                  We are using the pins 9 and 10 for the Chest Electrode V2  in our own board, but not getting any output from it. 

    Thks&Rgds,

    Uma mahesh

     

                  Please give us  some valuable suggestions to resolve these issues.

  • 0 in reply to umamaheswar peta
    TI__Mastermind 38745 points
    Hey Uma,

    Regarding the lead I & II noise issue, have you confirmed that the noise is not actually appearing at the inputs by probing the input lines with an oscilloscope? If they noise is not actually present, then the issue is likely to have something to do with how the data gets manipulated in the software. I've also seem issues appear when the timing of data collection over SPI between the processor and the device becomes poorly timed. For example, if some host process takes too long and the controller does not collect the data quick enough in between samples, the data could become corrupted. My advice to debug such an issue would be to start by probing the SPI lines and making sure everything looks good there and then work your way through the code analyzing what happens to the data at every step.

    For the issue with the V2 output, it's likely that there is something awry with the SPI transaction that collects the data. It looks like this electrode will be measured on channel 4. Probe the SPI lines with an oscilloscope or logic analyzer and look to see if that data ever gets collected by the mircrocontroller. If it does, what happens to it after that?

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Expert 1370 points

    Hi Brain,

    Waveform is good for some period(Minimum 3 or 4 mins) ,later waveform is changing.  

    As per your previous suggestion, about SPI communication,there is no issues found in communication side.

     We are unable to monitor the input samples from DSO as it is in mV. 

     Now the issue is, the ADS1198 module works only for first few mins after switching on the Module.

     We doubt, it might be due to the internal heat of the module or improper functioning of components in it.

      Please give us some valuable suggestion to solve this issue.

    Rgds,

    Uma mahesh

  • 0 in reply to umamaheswar peta
    TI__Mastermind 38745 points
    Hey Uma,

    The ADS1198 is specified from 0 C to 70 C. Even if it was getting hot inside the module, I have never seen the issues like the ones you are describing be related to high temperature; especially since the lead I result always looks good. To rule out the ADS1198 as the source of these issues, is there a way for the raw data to be exported to a file before other processing to verify that it is coming back correct? If you could verify the raw data did not contain the noise or the spikes you are seeing, then you can ensure ADS1198 is not the source of the error. My approach to debugging the issue would be to check the integrity of the data at each step after the issue begins to occur so that you can root out what process is causing the corruption.

    Regards,
    Brian Pisani