ADS 1191 / ADS 1192 SPI

Alexander Goldin

Expert 1220 points

According to SBAS566A –DECEMBER 2011–REVISED SEPTEMBER 2012, page 8 TIMING CHARACTERISTICS:

SPI clock (SCLK) minimal value is 50ns, while Master clock (CLK) is above 400ns.

The question is: How SPI may be processed so fast, faster than master clock?

over 10 years ago

0 Brian Pisani over 10 years ago

TI__Mastermind 38745 points

Hello Alex,

The master and SPI clocks synchronize different processes. Data is converted, filtered, decimated and otherwise manipulated using the master clock. The serial clock simply shifts bits in and out of the interface. They are two separate processes that are (mostly) asynchronous and thus can be clocked separately.

Regards,
Brian Pisani

0 Alexander Goldin over 10 years ago in reply to Brian Pisani

Expert 1220 points

Thank you, Brian.

I understand and agree with you, but my question is who can synchronze SPI process FASTER than the master clock?

As far as I understand, the master clock serves as a base for every other clock in chip, so other clocks cannot be faster.

Am I wrong?

Thank you in advance.

0 Brian Pisani over 10 years ago in reply to Alexander Goldin

TI__Mastermind 38745 points

Hello Alex,

The internal master clock is not used for the SPI communication. The SPI clock is generated by the SPI master so there is no restriction on its speed based on the internal clock frequency of the slave.

Regards,
Brian Pisani

0 Alexander Goldin over 10 years ago in reply to Brian Pisani

Expert 1220 points

Brian, you are right.
I have marked your replies as answers.
Thank you.

Data converters

Data converters forum

ADS 1191 / ADS 1192 SPI