Input current on TVP5150AM1 RESETB pin

Stephen,

Are you able to completely disconnect from the Altera just to make sure there is not some strange back current of something else related to the Altera?

Are all your power supplies correct?

What exactly is failing with the reset?

Are you ensuring all supplies are up and stable before releasing reset?

Are you waiting long enough after reset before starting I2C transactions?

What is your 'normal' reset driver?

BR,

Steve

Dear Steve,

Here are the answers to your questions.

Q1. Are you able to completely disconnect from the Altera just to make sure there is not some strange back current of something else related to the Altera?

A1. No, we can't disconnect the FPGA, the best we can do is leave it unconfigured it so that all it's pins are tristate.

Q2. Are all your power supplies correct?

A2. IO_DVDD=3.26V, DVDD=1.74V, PLL_AVDD=1.74V

Q3. What exactly is failing with the reset?

A3. The TVP5150A does not acknowledge I2C commands.

Q4. Are you ensuring all supplies are up and stable before releasing reset?

A4. DVDD comes up at t=0. IO_DVDD comes up at t=4.8ms. PLL_AVDD comes up at t=351ms. The FPGA also powers up at t=351ms. The RESETB and PDN pins on the TVP5150A are driven from the FPGA. These signals remain at 0V until the FPGA is configured at t=351ms .

Q5. Are you waiting long enough after reset before starting I2C transactions?

A5. The I2C transactions start at t=351ms +<hundreds of ms> when the TVP5150A software driver loads.

Q6. What is your 'normal' reset driver?

A6. The FPGA powers up a t=351ms and PDN is driven high permanently in the FPGA. RESETB also drives high at t=351ms.
At t=351ms+<hundreds of ms> the TVP5150A software driver pulses RESETB low for a few ms and there is a 20ms delay before the software driver starts I2C transactions.

Yours sincerely
Stephen Blake

OK, let me clarify the 'disconnect the FPGA'. I really only meant the reset signal. Can you either lift the TVP reset pin from the PCB or cut the trace so it is isolated from the FPGA and repeat your pull down current measurement?

Are you able to cycle the reset signal either through the FPGA or manually (similar to your 10K experiment but with a hard short to ground) to see if that clears the I2C issue?

Are you sure the FPGA output pin is 0V during configuration? I would expect it to be tri-state during configuration. Make sure there is truly a driven low period before releasing high.

BR,
Steve

Dear Steve,

We will look into cutting the trace from the FPGA to RESETB on the TVP5150A.

Q7. Are you able to cycle the reset signal either through the FPGA or manually (similar to your 10K experiment but with a hard short to ground) to see if that clears the I2C issue?

A7. We have tried cycling RESETB under FPGA control and this does not fix the intermittent problem.

Q8. Are you sure the FPGA output pin is 0V during configuration? I would expect it to be tri-state during configuration. Make sure there is truly a driven low period before releasing high.

A8. For t<351ms the RESETB pin is at 0V. Power is applied to the FPGA at t=351ms. There is an interval where the FPGA has power and is configuring. During this interval the RESETB pin used to float high (before it was tied to 0V with the resistor) as you correctly expected. Then, as the FPGA works normally, the RESETB pin is driven high or low depending on the state we set up in the FPGA. We hypothesize that our fix (weakly pulling RESETB to 0V with a resistor) works because it prevents RESETB floating high during the time the FPGA is configuring when its pins are tristate. Also, we hope for a fix which does not involve fitting a resistor to the PCB.

Yours sincerely
Stephen Blake

This really sounds like the timing of reset is not quite what you are expecting. Can you possibly capture the reset signal & I2C clock or data on an oscilloscope (without the pull down resistor) to make sure it is a solid low, then solid high before I2C starts up?

If adding the resistor fixes the issue then it is definitely a reset timing issue I think.

BR,
Steve

Dear Steve,

Q9. OK, let me clarify the 'disconnect the FPGA'. I really only meant the reset signal. Can you either lift the TVP reset pin from the PCB or cut the trace so it is isolated from the FPGA and repeat your pull down current measurement?

A9. The RESETB trace is under the TVP5150A and then it goes to an inner layer, so we cannot cut the trace to isolate the RESETB signal from the FPGA. However, we could isolate the PDN signal from the FPGA. We have experimented with pulling PDN to ground through a resistor and the current sourced by PDN is also 120uA which is larger that then 20uA specified in the TVP5150A data sheet. We would be able to cut the track from the FPGA to PDN on the TVP5150A to isolate PDN from the FPGA and measure the current sourced from PDN.

Q10. This really sounds like the timing of reset is not quite what you are expecting. Can you possibly capture the reset signal & I2C clock or data on an oscilloscope (without the pull down resistor) to make sure it is a solid low, then solid high before I2C starts up?

A10. We've captured RESETB and I2C SDA and SCL on the 'scope and everything seems in order.

I have a question. Recall that my answer A4 said:

A4. DVDD comes up at t=0. IO_DVDD comes up at t=4.8ms. PLL_AVDD comes up at t=351ms. The FPGA also powers up at t=351ms. The RESETB and PDN pins on the TVP5150A are driven from the FPGA. These signals remain at 0V until the FPGA is configured at t=351ms .

Is it possible that PLL_AVDD is applied too late and so there is 350ms in which some junctions in the device are forward biased causing I2R stress in the device with the result that the reset circuitry has been damaged?

Yours sincerely
Stephen Blake

Dear Steve,

A9 addition
We've now cut the track from the FPGA to PDN on the TVP5150 and pulled PDN to ground through a resistor. The PDN pin is now at 0V, the current out of the PDN pin is consistent with the 20uA in the TVP5150A data sheet. The large current that prompted this question is now understood as coming from the FPGA.

The delayed power should not damage the device.

Is the 120uA measurement on the PDN signal with or without the cut trace to the FPGA?

There should be no I2C signal transitions until the reset sequence is complete, but I think you have already checked that.

Is PDN controlled correctly with respect to reset, power, I2C etc...?

Can you try pulling PDN high on a bad board to see if it changes the behavior in any way? (not the current draw, but the I2C failure)

I can't think of any other reasons why a good solid reset should not correctly reset the TVP.

BR,

Steve

Good news.

Is your reset issue in general now fixed too?

BR,
Steve

All I can suggest at this point is to ensure that the reset low period, then reset high before I2C activity are something really long (x100s ms) as a test to see if reliability increases. That might point you in the right direction, i.e. power glitch or something similar.

I have never seen this issue before.

BR,
Steve