• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 702 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC10D1500 DCLK quality

Heedo Kang
Prodigy 20 points
Other Parts Discussed in Thread: ADC10D1500

I want to ask you what is the critical factor to make the DCLKI/DCLKQ of ADC10D1500.

I made the ADC board using ADC10D1500 with integrity guides, such as building stable power supply, low-distorted sampling clock, low impedance ground, and isolation between digital and analog ground, etc.

However, the DCLK quality is very poor when I turn on the board and insert the pure sampling clock to the ADC. Actually, the sampling clock has almost ideal quality at the ADC input ports..

I think, therefore, the converted digital information from ADC could be guaranteed at the receiver (FPGA) due to the poor quality DCLK.

Such Rtrim resistor or Vbg or etc. would be key factors to the DCLK generation?

  • 0
    TI__Mastermind 20541 points

    Hi Heedo,

    Here are some key things to keep in mind, while routing DCLKI/DCLKQ (LVDS signals).

    1.  If LVDS signal lines (Data, DCLKI, DCLKQ, ORI and ORQ) are long and in a noisy system. It may be necessary to select the higher VOD. Please follow the Converter Electrical Characteristics – Digital Control and Output Pin Characteristics table on page 23 of the datasheet.
    2. LVDS signal lines are always terminated with a 100Ω resistor placed as close as possible to the receiver (FPGA) input.
    3. High speed data paths and DCLKI/DCLKQ signals should be routed to have same length.

    Also want to point out, we don’t recommend isolating analog and digital ground, a single continuous ground plane (for both digital and analog grounds) or multiple planes should be used.

    Can you please share the schematic of the entire ADC related circuitry?

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 20 points

    Thank you, Neeraj.

    It was a termination problem at the receiver, I think.

    After the internal termination at the receiver, the reciever could sample the digital signals.

    However, the sampled signal is wrapped.

     

    For the application issue, 10-bit ADC is used as having 8-bit resolution (2-bit LSB is not used).

    When I insert the analog signal having single tone to the ADC input, the output digital signals are sampled at the receiver (FPGA) and these are dumped to the memory to figure out the input signals. The dumped signal seems like wrapped.

    Is it due to the MSB issue?

     

  • 0 in reply to Heedo Kang
    TI__Mastermind 20541 points

    Hi Heedo,

    I have attached the excel file which show the transfer function of an 8 bit ADC. The first column shows offset binary value (data) coming from the ADC. Second column show the equivalent decimal number for each binary code. The third column is the signed decimal values which are calculated by subtracting 128 from corresponding decimal values in the second column. It looks like there might be a computation error in FPGA code used to calculate decimal value or signed decimal value from the binary code.

    Regards,

    Neeraj

    8 bit offset binary to decimal.xlsx