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ADS131 Test Signal Period and Missing Data Investigation

Sean McDaniel
Prodigy 60 points
Other Parts Discussed in Thread: ADS131E08EVM-PDK, ADS131E08

All,

I'm trying to get a handle on the ADS131 square wave test signal. I'm collecting data from an ADS131 over SPI from a MSP430 microprocessor and writing to an micro-SD card (using the F5529 Experimenter's Board). Everything's being driven by an external oscillator at 2.0 MHz.

My problem: there may be missing data. I know there must be missing data, because based upon code changes, I get different periods (I write to disk, pull the data, and plot it). The internal ADS131 test signal is supposed to 'pulse'---I'm assuming this is the period, please correct me if I'm wrong---at f_CLK / 2**21 or f_CLK / 2**20 depending upon set register settings. This gives a period (distance between two pulses) of either 0.95 or 1.91 seconds. I'm currently using the non-default setting of f_CLK / 2**20. Sampling rate is at 4ksp. I expect a difference of 3814 samples period. I'm measuring differences of 1970 with fluctuations depending upon how I write the data to disk.

I know the details are a bit simple for exact advice, but I'm hoping you can help me with the following.

1. Do the periods that I've mentioned make sense? Around 1 to 2 seconds for the internal square wave.

2. Are there good strategies for quantifying missing data?

I can provide further details if necessary.

Thank you,

Sean

  • 0
    TI__Mastermind 23235 points
    Hello Sean -
    The ADS131E08 test signal should be a internally generated square wave. For reference, you can see the signal in Section 4.4, Figure 16 of the ADS131E08EVM-PDK user guide.

    Keep in mind that based on your sampling rate, you may get variation in the width of the square wave. The edge of the square wave may fall between samples, so you may have at least a datarate error in your measurements.

    Also make sure you are taking enough points to see the square wave. Faster datarates require more points to see the square wave, so make sure you are taking enough.
  • 0 in reply to Greg Hupp
    Prodigy 60 points

    Greg,


    Thank you for your reply. I read through the linked user guide. Can you confirm that the sampling rate is set to 4k for figure 16? That information isn't in the text.

    Given that we're driving the ADS1331 using an external clock at 2 MHz, we should use this clock (2 MHz) instead of the internal clock of 2.048 MHz for calculations, correct? We also have the test signal frequency (TEST_FREQ) set to 01 (pulse at f_CLK/2**20).

    I am also interpreting "pulse" in 00 = Pulsed at fCLK / 221 (default) to mean frequency. Is this correct? "Pulse" is ambiguous to me.

    I get the following expected periods in samples using the external(2MHz)/internal clock. Can you confirm these are correct?

    • 1ksps --> 524/512 samples
    • 2ksps --> 1049/1024 samples
    • 4ksps --> 2097/2048 samples
    • 8ksps --> 4194/4096 samples
    • 16ksps --> 8388/8192 samples

    Thank you,

    Sean

  • 0 in reply to Sean McDaniel
    TI__Mastermind 23235 points
    Hello Sean -
    There is no data associated with Figure 16, it is really just there for a graphical example.
    You are correct in that if you use a different input clock frequency; that clock is what you want to use for the calculation. 'Pulse', as you noted, is probably not the best description of the signal. The test signal should be a square-wave at the frequency selected. Additionally, please note that the test signal is intended as an example signal and really is not best used for calibration purposes.
    You might try to capture the SPI signals on a scope to see how well they line up and then can verify that you are meeting the timing specs of the device. As a caution: You are running the device fairly slow, but keep in mind that you have (1 status word + 8 channels) x 24 bits/word x datarate, which can be a much larger bit rate than at first glance; so make sure you do not run into bandwidth issues.
  • 0 in reply to Greg Hupp
    Prodigy 60 points
    Greg,

    Thank you for your response. I have one last item I'd like to confirm.

    If I change the external clock, I'll also change the sampling rate, correct? If the external clock is 2 MHz, the sampling rate will be decreased by the ratio 2/2.048.

    In this scenario, the number of samples per period is constant (e.g. 524, 1024, 2048, etc.) regardless of the external clock.

    Regards,

    Sean
  • 0 in reply to Sean McDaniel
    TI__Mastermind 23235 points
    Hello Sean -
    The ADS131E08 is a delta-sigma ADC, also known as a over-sampling converter. The benefits of delta-sigma converters arise from the fact the the input signal is over-sampled (at fMOD) and the resulting datastream is then decimated down to the actual output datarate.
    From page 15 of the data sheet, fMOD = fCLK/2; the output datarate, fdr = fMOD/OSR. OSR (over-sampling ratio) is the setting of the DR bits in CONFIG1 register. Table 4 of the datasheet shows the datarates for each of the settings assuming fCLK = 2.048MHz.
    So based on this DR = 000, OSR would be 1.024MHz/64SPS = 16. The other values can be calculated similarly; each OSR value for this converter is an increasing power of 2.