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Bit CLP mode enable for LM98725

Elnur Babishov
Intellectual 895 points
Other Parts Discussed in Thread: LM98725

Hello!

We try to use AFE LM98725 in our image board. We can not clearly understand some about register: page 0, addr 3, bit 5.

Bit 5 - Bit CLP mode enable.

What does it mean?

Thanks.

  • 0
    TI__Mastermind 22825 points

    Hello,

    Regarding your question on LM98725 CLP mode Enable:

    When enabled, Bit CLP mode closes the input clamp switch during the reference period of every pixel in the line. 

    It is similar to what is shown in Figure 10, but instead of being on during the CLPIN period (and gated by the SAMPLE timing signal) the Bit CLP mode is enabled every pixel during the line, but only during the CLAMP timing pulses. It is used to DC restore the AC-coupled input on every pixel. Please note that enabling the Bit CLP mode will degrade noise performance and should not be invoked if not otherwise necessary.

    Regards,

    Hooman

  • 0 in reply to Hooman Hashemi
    Intellectual 895 points

    Hello, Hooman!

    Thank you for your answer.

    Elnur.