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ADS1278 maximum sample rate

Val Safran
Prodigy 30 points

Hi,

I have some trouble to understand what maximum sample rate I can achieve if I am using frame-sync serial interface, TDM fixed point mode. I need to meet 120K sample per second and I am planning to run 37MHz clock.

from table 16, I see that in case of Mode selection for high speed rate and clockdiv = 1, my SCLK will be 1/4 of clock and I think that I can make 120KS/s in that case.


Please advise to me

 

Thank you,

Val

  • 0
    Prodigy 30 points
    I think I find that in High-Speed mode the SCLK can be same as CLK.
    So that means that I can use frame-sync serial interface, TDM, fixed point mode as fast as CLK or 192 clocks to shift out all 8 channels. (the frame size is 256 clock for 144K samples per channel)
  • 0 in reply to Val Safran
    TI__Guru 66466 points
    Hi Val,

    Thanks for your question.

    In High-Speed Mode, you may use CLK = SCLK = 37MHz. Your output data rate will be 144kSPS. If you scale the CLK down to 30.72MHz, you can achieve an output data rate of 120kSPS.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 30 points

    Hi Ryan,

    Thank you. I got it.

    I wasn't sure about A/D ability to sample it in time for frame-sync serial interface.
    Obviously it simplify PCB design, since I will use only 1 trace from the chip. (I am planning to use FPGA to interface with A/D)

    Thank you,

    Val