This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DVDD and fCLK limitations for ADS1278

Other Parts Discussed in Thread: ADS1278

Hi,


On page 26 of the datasheet for the ADS1278, Table 7, a clock frequency range is given for a certain DVDD. The language indicates this is only for maximum data rate but the table seems to indicate that this is the only valid frequency range for a given DVDD. Can you use a DVDD of 2.1V and a clock slower than 32.768 MHz (with a lower data rate)? The language indicates you could drop all the way down to 100 kHz with a DVDD of 2.1V. Is this correct?


Thanks,

DJ

  • Hi DJ,

    Thanks for your post.

    DVDD must be kept between 1.65V and 1.95V for CLK < 27MHz in order to meet datasheet performance. You can scale the master clock from 100kHz up to 37MHz in High-Speed Mode, as long as you keep these conditions for DVDD and Vref in mind. Note that these restrictions apply to High-Speed Mode only.

    I hope that clarifies this section for you.

    Best Regards,