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The timming of ADS1281

user4363186
Prodigy 80 points

The datesheet shows that "Note that a delay of 24 fCLK cycles is required between each byte transaction."in page 31.We want to know the timming of the delay of 24 fCLK cycles.

Whenever the command of WREG or RREG is sent ,the DRDY can not output anything.

If the  false timing of the 24fCLK cause no output of the DRDY.

  • 0
    TI__Mastermind 44680 points

    Hi,

    I'm not sure I understand your question. If you asking if this delay is required, yes it is needed for the ADC to decode the incoming command.

    With this device you need to send the SDATAC command (to exit RDATAC mode) before reading and writing to the device registers. You cannot change the settings mid-conversion. Therefore, it should not be a problem to miss the /DRDY signal, as you are not converting while modifying the register settings.

    Best Regards,
    Chris