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ADS5401 interleaved ADCs

David Sweigart
Prodigy 130 points
Other Parts Discussed in Thread: ADS5401

I'd like to verify my understanding of the ADS5401 interleaved ADC pair's operation.  I've read through the ADS5401 data sheet (SLAS946A - APRIL 2013 - REVISED JANUARY 2014), and, from the diagram on p. 24, I see that the interleaved ADCs operate 180 degrees out-of-phase from each other.  I interpret this to mean that one of the ADCs samples on rising edge of the Fs/2 clock, while the other samples on the falling edge.  If this is correct, I would expect the ADS5401's DA[11:0]P/N output to always begin with the output from the same interleaved ADC.  Is that correct?

In other words, let's suppose the two (physical) ADS5401 interleaved ADCs are named "ADC A" and "ADC B".  After power up, the DA[11:0]P/N output will then alternate between data samples digitized by ADC A and by ADC B.  Is it true though that the first ADC sample on the data lines always comes from, say, ADC A?  Or does the ADS5401 output sometimes start with ADC A's data and, at other times, with ADC B's data?  If the former is correct, I'd like to confirm that I could collect the even- and odd-numbered ADS5401 samples from data collected under different conditions (e.g., after multiple power-cycles, hardware resets, etc.) and be assured that each sample set is data from the same (physical) interleaved ADC.

Thank you in advance for any help in understanding the interleaved ADC operation.

  • 0
    TI__Mastermind 29220 points

    Hi,

    If the sync input is provided to the ADC to internally reset the internal clock dividers, then yes the same interleaved ADC will always go to the same edge of the DDR output clock.  From the designer:

    "Once the sync pulse is provided, all relevant clks reset to the correct phase.  So, to answer the customer’s question, the answer is yes."

    But even if the sync input is not provided, we believe the interleaved ADCs will still always go to the same DDR clock edge but we haven't tested for this.  Again, from the designer:

    "After looking at all the schematics today, all the clocks are based off of one divider (in the global clock circuit).    This is then fed to all the ADCs and the lvds data circuits.  In other words, all the internal clks are synchronized, which means that the lvds rising edge should always match one of the sub-ADCs, and he shouldn’t have a problem, even without sync.  im hesitant to give a guaranteed yes, however, since I don’t think this is really something we’ve tested in the lab. "

    Regards,

    Richard P.