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TSW1405 & ADS6142EVM

mael.guilbaud
Prodigy 190 points
Other Parts Discussed in Thread: ADS6149, ADS6148, ADS6142, ADS6145

Dear technical support,

I am trying to have ADS6142EVM working using FPGA board TSW1405 and "High speed data converter pro 3.0".

I succeed in running ADS6142EVM using break out PCB and logic analyzer, the sampled signal is very good on the logic analyzer.

When I use the TSW1405, the signal is very noisy on the GUI.

I have configure output of ADS6142EVM as LVDS with offset.

What I am doing wrong ? 

Do you have a guide which explain ADS6142EVM configuration in this use-case ?


Best regards,

Maël Guilbaud

Watt Consulting

  • 0
    TI__Mastermind 29220 points

    Hi,

    What is IHM?  I don't recognize that acronym.   You are looking at the FFT or the time domain data on HSDCPro?

    I think I need to make a new device ini file for you to add to the HSDCPro installation.  You are using the device selection ADS614x?  That device selection supports the ADS6148 and ADS6149 EVMs.   The EVM for the ADS6142 through ADS6145 is similar but for the lower sample rate supported, *and* the signal routing from the ADC to the connector is different.   The connector between the EVM and the FPGA is set up for 8 DDR LVDS pairs to support a potential 16bit sample, and the ADS6149 uses the upper 7 pair so that the data is msb-justified.   We have to shift the data down by two positions in HSDCPro in order to process it as 14 bit data.   The data bus on the older ADS6142 is not msb-justified, it is lsb justified.   When I look at the ADS6142-45.ini file for the TSW1400, I see that the data is not shifted down two positions but the upper two bits are zeroed out so that noise does't get onto the MSBs and corrupt the value of the sample. 

    I will have to make a new ini file for you called ADS6142-45.ini and test it first, but I think it will simply be the same as the ADS614x.ini with the line

    Data Postprocessing=0:2

    changed to be

    Data Postprocessing=2:16383

    I will have to find an ADS6142 EVM to try it out on.  The reason I need to test it first is that sometimes the LVDS is routed to the connector inverted if that means that the routes can route cleanly that way without having to cross.  I dont think that applies here, becasue I don't see the TSW1400 files having to account for such a thing, but still I should test before I send it.  You're welcome to make the change to your ADS614x.ini file and try it, with the understanding that I haven't tried it yet.

    Regards, 

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 190 points

    Richard,
    Thanks for your quick answer.
    I will try it on wednesday (I am out of lab tomorow).
    As soon as i have tested, I will let you know.
    Sorry for "IHM', it is a french acronym that means GUI. I was looking time domain.

    Best regards,
    Maël Guilbaud
    Watt Consulting

  • 0 in reply to Richard Prentice
    Prodigy 190 points

    Richard,

    I tried the .ini file modification without success.

    Have you got any other idea of settings I can try ?

    Regards,

    Maël Guilbaud

    Watt Consulting

  • 0 in reply to mael.guilbaud
    TI__Mastermind 29220 points

    Hi,

    I did round up an EVM for this device and try it on the TSW1405.  I found that the LVDS DDR clock signal *is* inverted compared to the ADS6149 EVM, either in the trace routing in the EVM or in the data sheet definition for the DDR data format.   I enabled the SPI interface for configuration register access and enabled the ramping test pattern.  I can clearly see that bit 12 is where bit 13 should be and bit 13 where bit 12 should be, and the same swapping all the way down to the LSBs.   I looked again at the ini files for the TSW1400 and I can see that the ADS6142 ini file does have one register setting different than the ini file for ADS6149 and that register is for the clocking configuration in the FPGA.  The FPGA on the TSW1400 has an option to invert the clock.

    I looked through the Verilog source code for the TSW1405 and there also is a register for inverting the DDR clock, so I will try that in the morning.  If it checks out then I will send an updated ini file.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    TI__Mastermind 29220 points

    Hi,

    Please see in the attached zip file a new ini file for the ADS6142/TSW1405 combination, plus a new firmware file.  After checking that the Verilog source code had an option for inverting the DDR clock, I found that the firmware file included with the HSDCPro is an older rev and did not support the feature.  So I looked for the firmware file with the date code to match the source and tried the new ini file.  That worked. 

    You know where to copy the new ini file, since you were able to find the ini files in ADC Files under TSW1405 Details.  Under TSW1405 Details there is also a firmware folder.  Copy this new firmware file there, replacing the one of the same name that is there now.  Then please give that a try.

    Regards,

    Richard P.TSW1405.zip

  • 0 in reply to Richard Prentice
    Prodigy 190 points

    Dear Richard,

    I had the chance to try TSW1405 & ADS6142EVM with your configuration files.

    It works properly ! Thank you ! 

    I really appreciate your reactivity.

    Regards,

    Maël Guilbaud,

    Watt Consulting