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ADC12J4000 Lane rate

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: ADC12J4000

Hi

My cutomer is using ADC12J4000.
He wants to use with the following condition.
Is this possible?

- Device clock : 3.6GHz
- 8 lanes output
- M=8　S=5　N'=12
- Not decimation (law data use at FPGA)

Could you let me know the calculation formula for lane rate?

Best regards
Shimizu

  • 0
    TI__Mastermind 44680 points

    Hi Shimuzu

    The easiest way to find the output lane rates is to look at Table 11 in the ADC12J4000 datasheet. The device has fixed output rates specific to each Decimation factor setting, as well as the formatting. The available rates are 1x, 1.25x, 2x and 2.5x the input DEVCLK frequency. 

    For No Decimation, the output lane rate is always at 2x the ADC device clock frequency, so in this case the rate would be:

    2 x 3.6 GHz = 7.2 Gbit/sec on each of the 8 lanes.

    The calculations for each mode can be fairly complicated, especially for those modes where Tail bits are added to optimize the link data rate to match the available output rates.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Guru 11235 points

    Hi Jim

     Thank you for your support.

      I understood

    Thanks

    Shimizu