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ADS1299 RDATAC Usage Status Register



In RDATAC mode ,the DOUT pin returns 216bits, and the first 24 bits are Status Register, But what is Status Register?

  • Hey Tracy,

    The status word contents are described on page 27 of the datasheet as "1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO register". Let us know if you have any more questions.

    Regards,
    Brian Pisani
  • Thank you very much!

  • Hey Brian:
    I have another question. I received 216 bits during DRDY remains high. It's 27 bytes, right? And the first three bytes correspond to Status Register. But what about the left 192 bits? For example , the 27 bytes are B[0], B[1]...B[26]. So CH1 correspond to B[3],B[4],B[5], such as
    ( (B[3]<<16) +( B[4] << 8) + B[5]). Am I right?

    Thank you for your time!
  • Hey Tracy,

    That's absolutely right. If you were trying to take the bytes you receive from the device and concatenate them into another data type like 32-bit integer, then the code you'd write would look something like that. However, remember that negative numbers will be in two's complement format so you'll have to account for the sign when you format the data into something your compiler likes.

    Regards,
    Brian Pisani
  • Hi, Brian:

    I short the INP and INN, and the results I got have many 0,it that correct?  And I get the wave of DRDY and SCK by scope. The blue line is DRDY, and the yellow line is SCK, but what's wrong is that during the DRDY remains high, there are only 14*8 period of SCK, not 27*8, do you know why ?

  • Hey Tracy,

    I actually doubt that you'd get all zeros with an input short measurement. You're likely to measure a small offset and noise. If the data is coming back as all 0x00s, then something is not happening the way it should. Check the DOUT line on the scope to see what is actually coming out of the device during data collection. Make sure the device is in RDATAC mode and that the channels you want to read from are powered on.

    That image of DRDY looks right. DRDY will fall low when a new conversion is ready, then come back high on the first falling edge of SCLK. As for the number of SCLK periods, that is definitely a microcontroller issue. Unfortunately I wouldn't really be of much help when it comes to microcontroller specific questions.

    Regards,

    Brian Pisani