Hello.
Is it possible to connect one ADC12J4000 ADC to two Kintex-7 FPGAs (lanes 0-3 of JESD204B link to first FPGA and lanes 4-8 to second FPGA)?
Assuming both FPGAs have same clocks.
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Hello.
Is it possible to connect one ADC12J4000 ADC to two Kintex-7 FPGAs (lanes 0-3 of JESD204B link to first FPGA and lanes 4-8 to second FPGA)?
Assuming both FPGAs have same clocks.
Hi Valentin
If you are capturing data for the purpose of evaluating the ADC12J4000 device, we recommend you use the ADC12J4000EVM along with either the TSW14J56EVM or TSW14J10EVM+Xilinx-VC707 for data capture. Either of these platforms can be used with High Speed Data Converter Pro to evaluate the ADC device performance.
If you are designing an end product it would be best to connect the ADC to a single FPGA. This is the normal configuration that the Xilinx JESD204B firmware is intended for. If there is a specific reason you need to use multiple FPGAs for data receive, I recommend you work with the Xilinx IP support team to determine whether the firmware can support the SYNC~ combining necessary to connect multiple data RX devices to a single TX device.
Best regards,
Jim B