ADS42LB69 CLOCK INPUT LVDS ac-coupled

Hi Masa,

1) Clock amplitudes as low as 0.2Vpp can be used but the SFDR and SNR will degrade at low clock amplitudes. Refer to Figure 58 in datasheet for more information. The maximum clock amplitude is set by the absolute maximum rating of 2.1Vp. Refer to section 7.1 of datasheet.

2) LVPECL is preferred over LVDS because of the higher output swing you can get from LVPECL compared to LVDS.

Thanks,

Eben.

Hi Eben,

Thank you very much for the answers.

May I have anote question?

What is clock input condition (LVPECL or other? Amplitude? Input frequency?) of Electrical Characteristics in Datasheet?

 

Best regards,

Masa  

 

Hi Masa,

For most of the measurements, a sine wave AC coupled clock was used with nominal amplitude of 1.5Vpp. But the performance is expected to be the same with LVPECL ,  LVDS, or LVCMOS clock.

Thanks,

Eben.

Hi Eben,

Thank you very much four your answer.

Best regards,

Masa

Hi Eben,

I am sorry for my trifle question again but I just want to confirm two points in the last your answer;

1) Your answer : "a sine wave AC coupled clock was used with nominal amplitude of 1.5Vpp."
It is 1.5Vppd (Vclkp-Vclkn) not 1.5Vpp at each Vclkp and Vclkn?

2) Your answer : "But the performance is expected to be the same with LVPECL , LVDS, or LVCMOS clock."
The same performance is expected at same 1.5Vppd with LVPECL and LVDS, and 1.5Vpp with LVCMOS clock?

Best regards,
Masa

Hi Eben,

May I have your answer?

Best regards,

Masa

Hi Masa,

1) The 1.5Vpp is Vclkp(peak) - Vclkn(peak). Normally the sine wave clock is single ended at 1.5Vpp and a transformer is used to convert it to differential for the ADC so that the peak to peak swing stays the same.

2) For the same performance but using an LVPECL clock, we recommend 1.6Vpp, for LVCMOS, we recommend 1.5Vpp and LVDS should be 0.7Vpp

Thanks,

Eben