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ADS1271 - Output is always zero

Other Parts Discussed in Thread: ADS1271

I'm attempting to get data from an ADS1271 converter but the reading is always zero. The ADC is being used in high resolution mode with SPI format.

I'm using the SPI peripheral on an EFM32 microcontroller. My code transmits 0xFE (MSB first) to create a SYNC pulse along with some SCLK cycles at 1MHz.

Based on the datasheet, I thought that DRDY would go high after the SYNC pulse for 512 CLK cycles (~19usec with CLK at 27 MHz) and then DOUT would start shifting the reading out on the falling edges of SCLK. Instead, DRDY goes high for ~36 usec and DOUT goes low for about the same time.

I'm using the center pin of a potentiometer (for testing) as the positive AIN for the ADC which gives a signal between 0 and 5V. Eventually I'll use the output of a difference amplifier with 0 to 5V swing. The negative AIN and the positive VREF are connected to a buffered 2.5V reference.

I've attached screenshots with schematics and logic analyzer output. Here is the code I'm using to talk to the ADC:

  do {

    /* Data reception from slave */
    /* ************************** */
    /* Setting up RX interrupt */
    SPI1_setupRXInt(receiveBuffer, RXBUFFERSIZE);
    /* Receiving data by transmitting dummy data to slave */
    USART1_sendBuffer(transmitBuffer, TXBUFFERSIZE);

    Delay(100);

    /* Clearing the receive buffers */
    memset(receiveBuffer, '\0', RXBUFFERSIZE);

  } while (1) ;

  • Hello Bubbzilla, 

    I'm not immediately sure what the problem is. You mention that you expected /DRDY to go high for ~19us after the SYNC pulse is issued; however, this is not the expected behavior. /DRDY will go high immediately after SYNC goes low and it will remain high for a maximum of 129 conversions = 2.45ms. Your SYNC pulse seems to meet the timing requirements in Figure 50, but I do not see a reason why /DRDY does not immediately go high with the falling edge of SYNC.

    Does this occur all the time, or are you sometimes able to read valid data from the device? 

    Best Regards,

  • The output is always similar.
    Is it possible that pulsing SCLK while transmitting the SYNC pulse would cause a problem?

  • Hello Bubbzilla -
    Have you validated you timing against Figure 73 and Table 11? It doesn't look like your timing meets the required specifications for the SYNC pulse.
    Additionally, keep in mind that you need to begin reading data after the DRDY pulse happens. If you read data over a DRDY pulse, you potentially can get partial data from two different samples.