DAC8568 power-up and drive sequence

Hi Larry,

It looks like the codes you are using are correct.

The signal does look very noisy, so I would suggest to slow down the clock to ~1MHz or less. This will allow us to determine if this is playing a role in the matter. If you have a few spare capacitors, it would be great if you could use them to clean the digital signals even further, specially SCLK. Some devices have sensitivity to SCLK overshoot and can sometimes interpret it as false edges.

Some additional questions:
What is the digital input voltage?
What is AVDD?
What is voltage applied at /CLR pin?
Do you have a load on Vout? What size?

Thank you Eugenio. I think that the noise is most probably picked up by the probes and the wires I'm using to sample the signals; the paths between the FPGA and the DAC are quite clean and short.

However I've slowed down the clock to 5 MHz and apparently nothing changes. There is one interesting thing though: even the first command (reference power up) doesn't work all the times, in fact it works quite rarely. Most of the time the reference stays at 0V and this happens either at 25 MHz and 5 MHz. So you are probably right when you say that there is some electrical problem.

To answer to your further questions:

The digital input voltage is 3.3V (*)
AVDD is 5V
The voltage applied to CLR# pin is 3.3V
The load on the Vouts is mostly negligible (say some uA).

(*) The datasheet states that when supplied with 5V, Vih is 0.625*AVdd (3.125 V). It should be ok to use 3.3V logic levels. In fact I believed that this particular specification in the datasheet had exactly this meaning, i.e. "when you power the IC at 5V you can use 3.3V digital logic without the need to add voltage translators".

Never mind, Murphy stricked again. I was measuring the signals on duplicated pins of the FPGA (I've replicated them into some free FPGA pins connected to test points easier to access) and then I've forgot about this. Connecting the probes to the actual DAC pins, I've found out that the SYNC# signal is not driven and floats around 2V... probably this is why sometimes the first command (reference power up) was picked up, perhaps at system power up some parasitic capacitance was still "charging" and the voltage was slightly under 2V.

In the past days I've made some veery bad experiments and probably I've zapped the FPGA pin. I will fix this relocating the signal to another pin and then I will report if it works, just to close the status of this thread.

I'm glad everything was resolved. We are very intimate friends with Murphy as well so we know that he is not the easiest friend to get along with.

If you run into any other problems with your DAC, send us an email so we can help you handle him.