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Test Pattern for ADC12D1800

Catherine Gyselinck
Prodigy 40 points
Other Parts Discussed in Thread: ADC12D1800

Hello,

I am using a ADC12D1800 on a FMC161 mezzanine by 4DSP with a VC707 motherboard by Xilinx.  The ADC provides clock and data to the motherboard Virtex 7 through a FMC connector.

I provide the ADC with a 910MHz clock; it should forward a 227.5 MHz clock to the Virtex 7.  The FPGA MMCM successfully locks unto the clock, never looses lock and the MMCM divide-by-1 output clock on a SMA test point is at 227.5 MHz.  So far, so good.

I believe I successfully command the ADC to go to test pattern since I do see the test data on my pins when I request it.  However, the pattern is stuttered.  I see : 0004000000100008 six times in a row, followed by 0ffb0fff0fef0ff7 four times in a row.  This pattern always repeat. 

I am at a loss.  Any idea?

Thank you,

C Gyselinck

  • 0
    TI__Mastermind 20541 points
    Hi Catherine,

    There are three main things I would like to try:

    1. ADC12D1800 output data is always delivered in double data rate (DDR), so the DCLK frequency is half the data rate and data is sent to the outputs on both edges of DCLK; please make sure you are using both, the rising and falling edge of the DCLK to latch the data.
    2. DCLK-to-Data phase relationship can be 0 degree or 90 degree. Please make sure you have right setting for latching the output data.
    3. Try using a low frequency analog signal (10MHz) and look at output data to see if you observe duplicate pattern.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Prodigy 40 points

    Hi Neeraj,

    I am capturing the data DDR in the FPGA.

    I have played with the DPS bit unsuccessfully but I can try again.

    I have tried halving the clock frequency to the ADC and observed that the frequency of my MMCM output was also halved.  But the data pattern captured did not change: 0004000000100008 six times in a row, followed by 0ffb0fff0fef0ff7 four times in a row.  I can try to go much lower in frequency (10 MHz) to see if this helps.

    Thank you for your input.  Any other ideas are welcome.

    Catherine Gyselinck

  • 0 in reply to Catherine Gyselinck
    Prodigy 40 points
    Hi Neeraj,

    1. DPS bit
    I have tried setting the DPS and DDR bits in ADC register 0 to "11", then adding the TPM bit. No improvement.
    I have tried setting the DPS and DDR bits in ADC register 0 to "01", then adding the TPM bit. No improvement.

    2. Reduced Frequency
    I tried bringing the ADC clock down to 10 MHz but when I did so, my MMCM could no longer lock because I was outside its range. So tried 50 MHz and my MMCM locked. Everything ran much more slowly but the data was still as I stated above.

    Any other ideas?
    Should I be seeing 0ffb0fff0fef0ff7 ,0004000000100008, 0ffb0fff0fef0ff7 ,0004000000100008,0004000000100008, or

    0ffb0fff0fef0ff7, 0ffb0fff0fef0ff7, 0004000000100008,0004000000100008, 0ffb0fff0fef0ff7, 0ffb0fff0fef0ff7, 0004000000100008,0004000000100008,0004000000100008,0004000000100008?

    (I am trying to lock on the former.)

    Thank you

    Catherine Gyselinck
  • 0 in reply to Catherine Gyselinck
    TI__Mastermind 20541 points
    HI Catherine,

    You are right, you should be seeing the 0ffb0fff0fef0ff7 ,0004000000100008, 0ffb0fff0fef0ff7 ,0004000000100008,0004000000100008 test pattern,

    In the 3 point, I want you to use a 10MHz signal as an input to the ADC while keeping the CLK rate to be 910 MHz and observe the output pattern.

    Regards,
    Neeraj
  • 0 in reply to Neeraj Gill
    Prodigy 40 points
    Hi Neeraj,

    I have found the problem. The DDR capture by the iserdes inside the FPGA was not working well. Both clock an clockb were capturing the same even samples and the odd samples were never captured. This produced the 4/6/4/6... pattern I saw.

    I believe my iserdes clocking was according to spec so I have to work this out with Xilinx. But I now know the ADC is generating a correct test pattern.

    Thank you for your help,

    Catherine