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About ADS8568 behavor

HIRATA MITSUO
Intellectual 490 points
Other Parts Discussed in Thread: ADS8568

ADS8568 will have strange behavor.

ADS8568 has input triangle wave from +10 to -10.
It sometimes does not have conversion value, having constant sampling conversion.
ex) correct -6V,-2V,+2V,+6V,+10V
    behavor -6V,-2V,-2V,+6V,+10V
It looks like outputing old value.
And this behavor occurs both A0 and A1 or B0 and B1.

*see 'attached_ADC1.pdf'

CONVST_A/B/C/D,BUSY,-CS,-RD pin of ADS8568 is connected to FPGA.
All lines has EMI filter NFR21GD3302202L.
CONVST line has 1k ohm pull-down and all of CONVST_A-D connected to FPGA 1port.
Another line has 10k ohm pull-up.
It means that it has reason of signal delay.

We supposed for unsatisfaction of CONVST_A/B/C/D,BUSY,-CS,-RD sequence.
However, CONVST_A/B/C/D,BUSY,-CS,-RD sequence would have satisfaction by checking wave form and FPGA simulator.

*see 'attached_ADC2.pdf' and 'attached_ADC3.pdf'

So we have no idea why this behavor is caused.
Please tell me reason of this behavor.

Best regards,
Mitsuo Hirata

1031.attached_ADC.pdf

  • 0
    TI__Guru**** 181021 points

    Hi Hirata-san,

    When using the ADS8568 with the internal conversion clock, there will be some uncertainty as to when the conversion starts with respect to the application of CONVST.  Can you add the equivalent of one conversion clock cycle delay (~85ns) in your FPGA before you start to read data?

  • 0 in reply to Tom Hendrick
    Intellectual 490 points

    Hi,Tom-san

    Thank you for your answer.
    I will request for customer to add clock cycle delay.

    However, I want additional information.
    What is meaning of 'with respect to the application of CONVST'?
    I want example of its action.

    Best regards,
    Mitsuo Hirata

  • 0 in reply to HIRATA MITSUO
    TI__Guru**** 181021 points
    Hi Hirata-san,

    If the conversion clock is external, you can easily synchronize the application of the CONVST input to the conversion clock source and therefore ensure you have the same number of clocks per conversion cycle. When the internal conversion clock is used, there is no way to sync up the CONVST inputs so you are going to have +/- 1/2 clock cycle of uncertainty for the point at which the conversion completes (BUSY going low). If you trigger on the rising edge of BUSY and look at the falling edge over time, you will see a dither of 1 conversion clock. If the conversion results are read out before all conversions are complete, you can have the chance of getting repeated data.
  • 0 in reply to Tom Hendrick
    Intellectual 490 points
    Hi,Tom-san

    Thank you for your answer very much.

    > you are going to have +/- 1/2 clock cycle of uncertainty for the point at which the conversion completes (BUSY going low).

    I want to check for delay action.
    Which does tBUCS or tCSRD need to add delay of, 1 clock cycle or 1/2 clock?

    Best regards,
    Mitsuo Hirata
  • 0 in reply to HIRATA MITSUO
    TI__Guru**** 181021 points
    Hi again Hirata-san,

    BUSY goes active with the application of CONVST, that part of it is asynchronous to the conversion clock. BUSY goes low only after the conversion is complete which is dependent on the internal (or external) conversion clock. If the conversion clock is internal, there is +/- 1/2 clock uncertainty in where the conversion actually begins, and therefore ends, before you can read valid data. Look at BUSY on a scope and you'll see what I mean. The delay is not really tBUCS or tCSRD, it's actually tCONV from the rising edge of CONVST_x.
  • 0 in reply to Tom Hendrick
    Intellectual 490 points
    Hi,Tom-san

    Thank you for your quick response.

    > it's actually tCONV from the rising edge of CONVST_x.
    I understood it.

    I had new information from customer yesterday.
    When tCSRD had delay 50ns, strange behavior was not found.
    If internal clock's behavor has only BUSY's rising and falling edge, it looks that it needs to read data after 1/2 clock of falling edge.
    Because read timing is only after falling.

    Please give me your advice about delay action of tCSRD.

    Best regards,
    Mitsuo Hirata