LM97600 SYNC problem

Hi Doojin

Please note that the Serializer Test Patterns (selected at Register 14h) are directly output at the serializer outputs and are not 8b/10b encoded. The SYNC training pattern, ADC Test Pattern data and real ADC data are all 8b/10b encoded. Given what you describe it seems like the problem may be related to your 8b/10b decoding in the data receivers.

Another thing to check is whether the error rate is dependent on the ADC clock frequency and the resulting data rate. If the errors are reduced at lower clock rates then the problem might be related to the signal quality of the serial data received at the FPGA. If this is the case you can try adjusting the settings in register 11h (Serial Config 1). If the serial links are DC-coupled from the ADC outputs to the FPGA inputs, it is important to set the Output Offset Select value so that the common mode output is within the common mode range of the FPGA receivers. If this is properly match, increasing or decreasing the Output Voltage Select value may help. Finally, increasing the De-emphasis setting may help improve the signal quality at the receiver if the signals are on a lossy substrate like standard FR4, and the link is a significant distance.

Please check these things and let me know what you find.

Best regards,

Jim B

Dear Jim,

Thank you very much for your kind reply.

I have tested all the things that you mentioned, but still the training sequence(SYNC=1) have some errors.

First, I receive the 8b/10b encoded data without 8b/10b decoding.

So, the 8b/10b decoder is not related to this problem.

And, I have reduced the ADC clock as 1.25G (ADC running as 2.5G) and tested.

But there is no difference on error rate.

Also, I have changed the "Output Voltage Select" and "De-emphasis" in register 11h, but has no effect.

The serial links are AC-coupled, so changing the "Output Offset Select" value has no effect and I have already matched the value.

I have excerpted some captured data from my "SignalTab" waveform.

The following data is input data from ADC lane 7

00110100101101000001 10110100101010111110 10110100101101000001 00110100101000101101

10110100101010111110 00110100101101000001 00110100101010111110 10110100101111010010 ...

The following is manually 8b/10b decoded data from above data.

0

0110100101:D5.6(+)

101000001 1:K28.5(-)

0110100101:D5.6(-)

010111110 1:K28.5(+):ERROR

0110100101:D5.6(+)

101000001 0:K28.5(-):ERROR

0110100101:D5.6(-)

000101101 1:K27.7(-)

0110100101:D5.6(-)

010111110 0:K28.5(+)

0110100101:D5.6(+)

101000001 0:K28.5(-):ERROR

0110100101:D5.6(-)

010111110 1:K28.5(+):ERROR

0110100101:D5.6(+)

111010010 0:K27.7(+)

This above 160 bits data is received repeatedly.

And there are some errors like above (some K28.5 packet : incorrect last bit)

The position of error has different to lane by lane.

Some packet in other lane has errors on first bit.

Some packet in other lane has error on n'th bit.

But, when I received the test pattern, all received data has no error.

I have set the test pattern as 11111111110000000000, 10101010101010101010, 10101010100101010101.

All above patterns are received well with no error.

So, it is very strange why the test pattern has no error but the training sequence has error.

Best Regards,

Doojin Han

Hi Doojin

I'm not sure what could be causing the errors in the training sequence.

Is it possible to look at the signal quality of the SERDES lanes at the input to the FPGA? Does the Altera FPGA transceiver you are using incorporate the EyeQ function? You could either use that feature, or a high speed oscilloscope to look at the signal.

Can you try slowing down the CLK frequency to see if that has any effect on the errors?

Best regards,

Jim B

 

Dear Jim,

I have solved the problem.
I have checked the input data by SignalTap (ChipScope as Xilinx) and the SignalTap sometimes gets incorrect input data.
The input training sequence itself was correct from beginning.
I have added the 8b/10b decoder and the received data was also correct. (FB C5 BC C5 BC C5 BC C5 ...)


Thank you for your sincere support.
Best Regards,

Doojin Han

Good new! Thanks for the update.