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DAC38J84 Configuration

Vincent GLOUX
Prodigy 40 points
Other Parts Discussed in Thread: DAC38J84

Hello,


I'm currently working on a project interfacing DAC38j84 and FPGA and i'd like to have some help with the configuration of the DAC.


The clocks to the DAC38J84 comes from LMK04828B.

DACCLK = 307.2 MHz

SYSREF = 9.6 MHz


I'm sending data with FPGA over 4 lanes (3072 Mbps on each lane).

I configured the DAC to have an update rate of 2457.6 Mbps.

Serdes Clock is at 3072 Mhz with a quarter rate configuration

When i read DAC registers, i see both DAC and SERDES PLL0 locked but i have 8b/10b error on all 4 lanes. config100-103 = 0x0703


On the FPGA side, i see syncab signal toggling but i can't establish a connection. Here is Data sent from FPGA between BC data

1C 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 7C

1C 9C 09 00 00 03 00 1F 01 0F 2F 20 00 00 00 43 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 7C

1C 41 42 43 44 45 46 47 48 49 4A 4B

I must have miss something in SERDES configuration but i can't figure what.

I'm attaching configuration file and screenshot from DAC3XJ8X GUI if someone can help me.


Thank you


dac_421.cfg

  • 0
    TI__Guru 72994 points
    Hello,

    One quick thing that you may try is to probe the SYNCB LVDS line. If SYNCB is logic HIGH, then sync is establish on the JESD. If it is logic low, it means that the JESD never achieved code group synchronization. Most likely the latter is the case, especially that you got 8b/10b error.

    I would check your FPGA is indeed in CGS mode and outputting valid K28.5 characters first.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Hello,

    Thanks for your response.

    I'm using sync_n_ab  and i'm seeing toggling in my FPGA as seen in the capture below :

    I've also seen /K28.5/ characters using an oscilloscope.


    It seems i have problem in ILAS Phase but those 8b10b error should be for CGS phase. Can i see syncb signal toggling if the DAC doesn't  decode /K28.5/ characters ?


    Vincent

  • 0 in reply to Vincent GLOUX
    TI__Guru 72994 points
    Hello,

    You may check the physical layer (SERDES) signal integrity by running some test patterns such as 0/1 pattern or PRBS patterns. This should bypass the JESD link layer and only testing the SERDES portion.
    The steps are the following:
    1. Select the type of SERDES test. You probably can start with a simple 0/1 pattern. (i.e. config61, bit14-12 = 001)
    2. Set DTEST = 0011 (config27, bit11 to 8). This routes the internal pass/fail signal to the external CMOS output ALARM pin. Logic high indicates failure, logic low indicates pass.
    3. Select the lane ID which you want to perform the test. (i.e. config27, bit14:12))

    You may refer to the GUI if you want a quick config: DAC3xJ8x Control -> SERDES and LANE configuration -> SERDES lane testing.

    Also, make sure you enable the lanes that you need in config74. For config73, make sure to program all the bits to zero to set all lanes to only link0. I.e. all the JESD lanes transfer data to one link. If they are set to anything other than zero, it is possible to get errors as well.

    Once you get the link established, we can run additional link layer test for further debug if needed.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 40 points
    Hello,

    The first test with 0/1 pattern was successful and i saw ALARM signal being deasserted when i sent the pattern.


    Then i tried to sent a PRBS7 and PRBS23 pattern but ALARM Pin stays high.


    My understanding is that link seems OK but output of SERDES is wrong for some reason. Can i get more informations with additional test between 0/1 pattern and PRBS ?


    Thanks
  • 0 in reply to Vincent GLOUX
    TI__Guru 72994 points
    Hi Vincent,

    THe PRBS7 and PRBS23 should be the standard pattern generated from linear feedback shift register. Some brief introduction can be found here:
    en.wikipedia.org/.../Pseudorandom_binary_sequence

    The fact that you send PRBS patterns and the ALARM pin stays high indicates there may be signal integrity issue. You may want to check on the scope to see if the eye opening is sufficient, both amplitude and period wise. Since the pattern becomes more random, the eye diagram should be worse due to ISI when compared to the standard 0/1 pattern.

    I would also double check your test sequence to see if they match the procedures described on section 7.3.19 and 7.4.2 of the datasheet.

    There is also an option for you to program your own 20bit pattern. This requires the use of JTAG port, and is not fully described here. I would first try out the default PRBS patterns before your own programmable pattern.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Please find some measurement made on the link between FPGA and DAC with attached screenshot.

    Thank you,

    DAC38j84_configuration.doc

  • 0 in reply to Vincent GLOUX
    TI__Guru 72994 points
    Hello Vincent,

    sorry for the late reply. The fact that SYNCB toggles from High to Low indicates that the JESD achieved CGS but not ILAS. The passing of the ILAS requires the LMFC setting on both the FPGA and DAC to be identical. Some of the additional things to check are K values and RBD values programmed on the DAC.

    When this situation occurs, please advise the alarm readings on the DAC GUI. This could help us out with further debug.

    Also, please check to see if the DAC analog core is working correctly. This could help us indicate if there are any potential board or component issues:
    The following test bypasses the incoming JESD data and uses the constant input + fs/8 mixer to generate a fs/8 tone at the output.
    1. config2, bit 2 = 0, bit 6 = 1: offset binary mode, mixer enable //Register set to 0x0040, address = 0x02
    2. config48 = 0x0000; all zero constant code //Register set to 0x0000, address = 0x30
    3. config13, bit15 = 1, enable fs/8 mixer you should see a full-scale tone at fs/8. If not, we will need to narrow down our search first on the DAC side and then move on to the JESD side. //Register set to 0x8000, address = 0xD

    Lastly, please advise the FPGA that you are using. Recently, one of our customer encountered a similar issue and ended up having to adjust the FPGA PLL settings in order to pass both CGS and ILAS stage. You may want to contact your FPGA support team to see if you are configuring the FPGA PLL/DLL correctly.

    -Kang
  • 0
    Intellectual 260 points
    Hi Vincent,

    Have you got the design finally working? We are experiencing very similar issue with Kintex-7 interfaced to DAC38J84 and would appreciate any hint.

    Thank you,
    Vlad.