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SPI clock polarity on ADS8317

Other Parts Discussed in Thread: ADS8317, CSD

I understand that the ADS8317 uses falling edges of DCLOCK to set up data, so that data should be sampled on the rising edges of DCLOCK.

The timing diagram looks like it should be OK to use either SPI mode 0,0 or 1,1 - that is, DCLOCK may either be idle low or idle high. However, the "Timing Characteristics" table contains the following line:

t_CSD: CS falling to DCLOCK low, max 0ns

t_CSD is shown in the diagram as the time between CS going low and DCLOCK going low. Do I have to interpret this as saying that DCLOCK is not allowed to be high when CS goes low, thereby ruling out SPI mode 1,1?