ADS1222 VDD Power ON sequence

Takumi-san,


Since the ADS1222 only has the single VDD supply, this makes it slightly easier to describe the power supply than those devices that have separate analog and digital supplies.

In general, you want the VDD to come up first before any other analog or digital inputs are applied. This will ensure that none of the other inputs are sourcing power through the ESD diodes in the device.

VDD should come up monotonically with the supply continuously rising. Small amounts of capacitance for decoupling will help (0.1uF), but larger amounts of capacitance (>10uF) are generally discouraged so that the device will power off quickly when the power is disconnected.

Note that this is a slightly older device and the power-on-reset was designed primarily for the power-up from a case when the device is completely off. Since the power-on-reset is set up based on an RC time constant, the VDD needs to return to 0V to reset the device.


Joseph Wu

Takumi-san,


I'm not sure exactly what is happening in your case. I would have thought that the Self-Calibration would have solved this problem. Normally, if there were some similar condition, I would have guessed that the stored calibration was disturbed by the intermittent power supply and the value stored is no longer correct. However, it's possible that the digital state machine is also wrong, although I've never seen this happening for the ADS1222.

In the past, we've tried to solve this type of problem for other devices by reducing all of the available charge that is near the device. That would include reducing the bypass capacitors and filter capacitors so that there isn't much charge to draw from when the power goes out. That's why I would recommend 100nF for bypass capacitors. As an example the bypass is 10uF, it may take many seconds for the charge to drain out before the VDD drops below the needed point to restart the power-on-reset circuit.

Another thing to do would be to check all the other connections to the ADS1222 to see if any of the other lines are still high when the power is removed. This would include all the analog input lines and the digital lines. If any of these lines still have charge, it may still be supplying it to the device, preventing the reset. If there are large filter capacitances on the analog inputs, they may also may be drawing charge.

One possibility would be to try remove the charge quicker by adding a resistive path to ground. By putting a 1k resistor from the VDD line to GND, you may have some extra current draw, but it will pull charge out of the circuit quicker.


Joseph Wu