• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 48 subscribers
  • Views 1342 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC37J82 LMF=124 settings

Ana S
Prodigy 65 points

Other Parts Discussed in Thread: DAC37J82

Hi,

I am trying to configure the DAC37J82 with the following settings: LMF = 124, x2 interpolation, A output channel, serdes line rate of 2457,6 Mbps, DAC data input rate 61.44 MSPS, lane 2 of DAC (L1 and M1 inputs).

DAC37J82 EVM is connected through FMC to a board with Lattice ECP5 FPGA.
The FPGA is sending sine wave samples. I can see in Lattice's Reveal logic analyzer that the link has passed the cgs and ilas phase and that it's in the data phase, but there is nothing on the DAC analog output. I sometimes get the FIFO read empty error in the DAC3xJ8x GUI, and sometimes none of the alarms for lane 2 are set.

I managed to get the analog output for the LMF=222 mode, line rate was also 2457,6 Mbps. Sine wasn't smooth in this case, I don't know why, but at least I got something at the output.

I attached the configuration file I used for LMF=222 mode, and LMF=124.

Any help regarding this issue would be highly appreciated.


Regards,

Ana

dac_124.cfgdac_222.cfg

  • 0
    TI__Guru* 83535 points
    Hi Ana,

    I will have to look into your config file in detail sometimes next week. In the mean time, you may check to see if the DAC core itself (excluding SERDES+JESD) is operating correctly

    The following test bypasses the incoming JESD data and uses the constant input + fs/8 mixer to generate a fs/8 tone at the output.
    1. config2, bit 2 = 0, bit 6 = 1: offset binary mode, mixer enable //Register set to 0x0040, address = 0x02
    2. config48 = 0x0000; all zero constant code //Register set to 0x0000, address = 0x30
    3. config13, bit15 = 1, enable fs/8 mixer you should see a full-scale tone at fs/8. If not, we will need to narrow down our search first on the DAC side and then move on to the JESD side. //Register set to 0x8000, address = 0xD
  • 0 in reply to Kang Hsia
    Prodigy 65 points

    Hi Kang,

    thank you for your reply.

    I tried the test you suggested, and yes, DAC core itself is operating correctly, there is a 15,3 MHz sine at the output.


    Regards,

    Ana

  • 0 in reply to Ana S
    TI__Guru* 83535 points

    Hi Ana,

    I found the problem with the RX/JESD mux setting (config95). Please see attached for proper RX/JESD mux configuration for Fdata = 61.44MSPS, 2x, 124 mode, and RX lane2 active.

    Basically, you will need to enable RX2 receiver to receive the SERDES data. Then, in config95, you will need to assign JESD lane 0 to look for RX2 data. 

    DAC37J82_2x_61p44Data_1lane_124mode_Fdac122p88MHz_Lane2RX.cfg

  • 0 in reply to Kang Hsia
    Prodigy 65 points

    Hi Kang,

    that's it! Thank you very much!

    I have one more question. I attached a picture of the sine output I captured with scope. Why isn't the sine wave smooth(er)? I'm sending 8 samples on 122.88 MHz, so I get a ~15 MHz sine wave. The samples are the following:  0x0, 0xA53E 0x8001, 0xA53E, 0x0, 0x5A82,  0x7FBF, 0x4A82.

    Regards,

    Ana


                       

  • 0 in reply to Ana S
    TI__Guru* 83535 points
    Hi Ana,

    you may notice that there are 8 steps on your waveform. This is mainly due to the DAC's sample and hold circuit. To get a smooth output waveform, you will need to attach a low pass (anti-aliasing filter) or use a higher sample rate after interpolation.

    See below app note for detail
    www.ti.com/.../slaa523a.pdf

    -Kang