We have been using DAC38J8XEVM board and because of some design constraints we needed to migrate to DAC38RF8XEVM. We have been experiencing some issues with DAC38RF8XEVM board so far. Here are the details:
1 – When configuring the DAC from the DAC38RF8X GUI software the LMK04828 clock generator PLL’s does not get locked, automatically.
2 – After configuration, the clock outputs of the DAC board are set to powerdown, namely DCLKOUT0, DCLKOUT12.
3 – After manually configuring the PLLs and clock outputs, we were able to have JESD link locked however no data is present at the output when sending from HSDC Pro GUI (with the software patch installed).
4 – The DAC itself gets hot.
We are using Xilinx KC705 with TI TSW14J10 interposer. Our setup uses internal PLL with 384 MHz reference clock. we have applied the modifications according to the user guide (installed C35, C36, C2 and C3 with 0.1uF, and removed C333, C334, C372 and C371) and used the exact parameters suggested in the document.
We did not have these issues with DAC38J8XEVM, given a similar procedure.
Have anyone experienced something similar? Can someone please address these issues?
Thank you,
