TSW 1400EVM for DAC 3482EVM HDL source code

Dimitar,

We are currently working on the legal issues with Altera regarding the distribution of this firmware. Hopefully we can send this or it will be on the web (TI or Altera or both) in the very near future.

Regards,

Jim 

Hi Jim,

Thank you for the answer.

Do you think this is a matter of days, weeks or months?

I think that having this hdl code will greatly simplify my work so i want to plan.

Best Regards

Dimitar Penev

Thank you Jim!
Dimitar Penev

Hi Jim,

I have managed to compile the TSW1400_LVDS_DAC HDL project in Quartus II Version 14.1.0.

I know that I should not expect support on this but probably what I am having unclear now is basic for you.

I am trying to use TSW1400 with DAC3482EVM board.
This combination is using DAC_SAMPLE_WISE.rbf firmware.

On the project root directory you have sent I see DAC_2W.rbf, DAC_SAMPLE_WISE.rfb, DAC3283.rbf and doc_default_minius_180.rbf.
So it seems all those are derived by the same HDL code, probably with some modifications.
A search in the forum seems to suggest some adjustments in ver/defines.vh file.
In this file i see some comments which probably are relevant:

`define FIRMWARE_VER 8'd2
// IID for all other is 129, for DAC3283 IID is 132 as DACCLK pinout is different, for DAC 2 wire 133
`define INTERFACE_ID 8'd133

I have tested all mentioned 129,132  and 133 value for the INTERFACE_ID but firmware I am building is not able to make my single tone test
(HSDC Pro (I/q multitone generator)+ TSW1400 +DAC3482EVM) working (always I get white noise like signal instead of a sine wave).
DAC_SAMPLE_WISE.rfb firmware provided with HSDC Pro works fine.

So my question.
How should I adjust ./ver/defines.vh (or some other files) in order to build DAC_SAMPLE_WISE.rfb ?

Edit: In the Quartus project provided by you I have found Quartus archive  "tsw1400_top_dac.qar"
(Looking at the code this seems to be the first version of the DAC firmware)
I have restored this archive compiled it and loaded the firmware in tsw1400.
Now I do get my sine wave but it has half the expected frequency. 

Thank you.
Dimitar

Dimitar,

We are looking into this for you.

Regards,

Jim

Dimitar,

Give this a try.

Regards,

Jim

TSW1400_LVDS_DAC_9_23_15.zip

Hi Jim,

Thank you for the new project files!

Unfortunately I still get white noise like signal instead of sine wave with it.

The only 'good' firmware compiled by me is the one derived by tsw1400_top_dac.qar
which is included in "latest_TSW1400_LVDS_DAC.zip" you gave me initially.
In that project I found `define FIRMWARE_VER 8'd1
Initially when I was testing this firmware I was geting sine wave with half the expected frequency.
I have tested again and now I am getting the correct frequency.
Probably I should assume that in the past I had CDCE62005 PLL issue and acctually the version 1
of the firmware is working fine for my sine wave test.

Still I would preffer to base my further development on the latest version which is expeced to be
the most compatible with current HSDC Pro.

Please advice.
Dimitar Penev

Hi Jim,

Today I have spent some more time on the TSW1400 setup.
Let me summarize what I have been given and what I have managed to achieve with it so far.

I have been given two zip files:

latest_TSW1400_LVDS_DAC.zip
- it contains   TSW1400_LVDS_DAC (noted as Rev 2, probably the latest code I have been given).
   I call this "Rev2latest"
- tsw1400_top_dac.qar (In the file "latest_TSW1400_LVDS_DAC.zip" i have found tsw1400_top_dac.qar wich extracts to another project noted as Rev 1).
   I call this "Rev1"

TSW1400_LVDS_DAC_9_23_15.zip
-This contains only one project, I'll call this "Rev2old"  

-----------
With original Rev1 I am able to load sine wave from HSDC Pro and generate it.

-----------
Rev2old is not working for me. After some trials I have manage to load sine wave however. 

It was necessary to do the following changes:
file ./ver/dacif_formatpdata.v
Original code:
...
always @(*)
begin
       case(dac_sel)
             2'b11 : shft_c = {din, din_r};
             2'b01 : shft_c = {din_remap2,din_remap};
             default : shft_c = {din_remap,din_remap2};
        endcase
end
...

I have modified to:
...
always @(*)
begin
       case(dac_sel)
             2'b11 : shft_c = {din, din_r};
            default : shft_c = {din_r,din_r};
        endcase
end
...
 

din_remap and din_remap2 is doing some data remapping which looks as experimental code for me. 

-----------
Rev2latest I am not able to make working.
From code perspective it looks most recent and trustful. 

Can you please help me with getting more trustful  code,
or selection the best one from what I have?

Thanks
Dimitar Penev

Dimitar,

 Our firmware development team determined that "Rev2old" can be considered as latest with the necessary modification in code.

Regards,

Jim

 

Hi Jim,

OK Thank you!

Regards
Dimitar Penev