ADS1296R DRDY Advances - timing problem

Hey Arun,

If you look at the ADS1296R datasheet in the electrical characteristics table in the "Clock" section, you'll see that the internal oscillator is only accurate to within 0.5%. This means that in the worst case, a single period of DRDY could be 3.98 ms which, as you said, accumulates over time to some quantity of delay versus the ideal clock period. However, the DRDY signal is a synchronization signal which is output from the device so that your host processor may synchronize collections of data from the device. I am certain that whatever processor you are using also has a tolerance on the clock frequency, if one is generated internally; and if not then the oscillator that generates the clock will have a tolerance. It is critical that the two devices be synchronized in software since neither clock will be ideally accurate.

In general, synchronization between a slave and master device can occur in one of two ways; either by polling or via interrupts. Polling is a software construct whereby the processor will wait in a "while loop" until the synchronization signal occurs, at which point the host will collect the data. An interrupt is a signal generated by a peripheral sent to the core processor to branch from its current process to respond to an external event. This method is generally more economical in terms of hardware resources since the processor does not have to simply wait for the slave to be ready; it can do other things while it waits. Let me know if you have any more questions.

Regards,
Brian Pisani