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ADC10080EVAL, how to modify to single end input and clk frequency.

Dear Specialists,

My customer has 10080EVAL and wants to confirm the specs under actual conditionl.

Could you please advise how to modify.

(1)The input signal is single end(0-3V). 

Also it must be used in single end, because current solution is single end and a board size is limited.

(2)CLK frequency is 24-72MHz.

The original clk is 12.5MHz.

Best regards,

Shinichi

  • Shinichi,

    If the customer would like to change the default Hardware configuration of the ADC10080EVAL so that the ADC can be driven single-ended, the customer can do the following:

    - Remove T1 and short pin pads 3 and 4 together with a small wire or 0805 0 ohm resistor.

    - Remove C9 but connect another 100pF capacitor from the VIN+ node of C9 to GND. You can probably get the GND connection by scratching off the solder mask off the top layer of the PCB

    - Place R2 with a 0 ohm, 0603 resistor

    Note that, for this configuration, the DC offset voltage of the input signal must meet the input VCM requirement of the ADC input which must be between 0.5 and 1.5V. If the customer's signal is between 0-3V, this might suggest a DC signal of 1.5V which is marginally within the range. From the datasheet, it appears that the device only supports up to 2Vpp input with the default VREF. A good solution would be to use a resistor attenuator to reduce the signal voltage swing and lower the input common-mode voltage. The customer can also AC couple the signal and provide the common-mode reference by placing a 1000 ohm resistor at R3.

    Regards, Josh

  • Dear Joshua

    Thank you for your reply.

    Your answer is used as a reference.

    About the clk OSC, I think it is removed and connect to outside clk.

    I appreciate your great help.

    Best regards,
    Shinichi