I am using the DAC PLL in the DAC38J82 with 160MHz RefClk input to produce 1920MHz DAC sample clock. The data sheet provides enough info to determine most of the register settings, but there is not enough information design the loop filter properly. The loop locks with any PLL_CP_ADJ current setting - at room temperature anyway, although there are definitely noise performance changes. I'm currently using the 800uA setting as a experimentally determined value that reduces the close in noise present with lower CP current settings while minimizing some odd spurs at 2MHz intervals that suddenly pop-up as CP current is increased toward maximum. Is there a way determine what the phase margin is for this design? Is there a design note or loop design tool somewhere that could be used by designers to determine this for themselves?
Second concern is the data sheet comment "Note that It is recommended to shift pll_vco by +1 to guarantee the VCO operation at hot temp environment. In case of cold temp environment, shift by -1 on the variable pll_vco is recommended." What temperature range is considered hot and cold. Also to clarify the wording...is it correct to interpret this value shift as a requirement for designs using the whole temperature range of the device in order to keep the PLL locked?
For reference, these are the PLL reg settings in the current design
pll_vcosel = 1 # Low Band VCO
pll_vcoitune = 10 # given in data sheet
pll_p = 0 # divide by 2 prescaler
pll_vco = 9 # solve quadratic for 3840 VCO freq
pll_n = 0 # ref divide by 1
pll_m = 11 # M = 12 for overall x12 PLL Ref->DACCLK
pll_cp_adj = 0x10 # 800uA
